Abstract: Provided are semiconductor dies and methods for forming semiconductor dies. A method includes forming a semiconductor die having under bump metal (UBM) pads in a dense region and in an isolated region; forming external electrical connectors in contact with the UBM pads; and limiting the external electrical connectors to a pre-selected vertical height.

Abstract: The present disclosure describes an example layout and method for cell placement in an integrated circuit (IC) layout design. The layout includes a first semiconductor structure having a first channel with a first channel width and a second semiconductor structure having a second channel with a second channel width different from the first channel width. The first and second channels can be in contact with each other. The method includes disposing a first diffusion region in a layout area and disposing a second diffusion region in the layout area. The first diffusion region can have a first diffusion region width and the second diffusion region can have a second diffusion region width different from the first diffusion region width.

Abstract: A substrate or IC chip is connected with a second substrate or IC chip. This entails disposing electrically conductive balls on electrical bonding pads of a surface of the substrate or IC chip to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip, and electrically and mechanically connecting the surface of the substrate or IC chip to the second substrate or IC chip using the BGA. An underfill material may be disposed on the surface of the substrate or IC chip around bonds between the balls and the electrical bonding pads. There may be at least two different types of electrically conductive balls in the BGA, such as solder balls and copper-based balls.

Abstract: The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.

Abstract: An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps.

Abstract: The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.

Abstract: The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed.

Abstract: An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps.

Abstract: The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: Disclosed is a solar cell including a substrate, an electrode layer disposed on the substrate, a p-type light-absorption layer disposed on the electrode layer, an n-type ZnS layer disposed on the p-type light-absorption layer, and a transparent electrode layer disposed on the n-type ZnS layer. The substrate can be immersed into an acidic solution of zinc salt, chelate, and thioacetamide, thereby forming the n-type ZnS layer on the substrate.

Abstract: A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided and a plurality of metal layers are formed on the substrate. A spirally patterned conductor layer is formed over and in the substrate and in the metal layers to produce a planar spiral inductor. A via hole is formed over and in the substrate and in the metal layers within the spirally patterned conductor layer, the via hole being formed by a through silicon via (TSV) process. Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface of the metal layers.

Abstract: A method for coating a layer of reduced graphene oxide (rGO) on the surface of substrate holes (especially holes with high aspect ratio) includes a serial wet process steps of hydrophilic treatment of the surface of the substrate, self-assembly of a silane layer, steps of grafting of a polymer layer, grafting of graphene oxide (GO), intercalation of metal ions, and intercalation of metal atom/rGO intercalation. The method further includes the decoration of conductive metals (copper or nickel tungsten) plug on the rGO layer in holes by electroplating process.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: Disclosed is a solar cell including a substrate, an electrode layer disposed on the substrate, a p-type light-absorption layer disposed on the electrode layer, an n-type ZnS layer disposed on the p-type light-absorption layer, and a transparent electrode layer disposed on the n-type ZnS layer. The substrate can be immersed into an acidic solution of zinc salt, chelate, and thioacetamide, thereby forming the n-type ZnS layer on the substrate.

Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.