Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: Disclosed is a solar cell including a substrate, an electrode layer disposed on the substrate, a p-type light-absorption layer disposed on the electrode layer, an n-type ZnS layer disposed on the p-type light-absorption layer, and a transparent electrode layer disposed on the n-type ZnS layer. The substrate can be immersed into an acidic solution of zinc salt, chelate, and thioacetamide, thereby forming the n-type ZnS layer on the substrate.

Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

Abstract: A thermoelectric structure for cooling an integrated circuit (IC) chip comprises a first type superlattice layer formed on top of the IC chip connected to a first voltage, and a second type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being different from the first voltage, wherein an power supply current flows through the first and second type superlattice layer for cooling the IC chip.

Abstract: A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided and a plurality of metal layers are formed on the substrate. A spirally patterned conductor layer is formed over and in the substrate and in the metal layers to produce a planar spiral inductor. A via hole is formed over and in the substrate and in the metal layers within the spirally patterned conductor layer, the via hole being formed by a through silicon via (TSV) process. Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface of the metal layers.

Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

Abstract: This invention discloses a thermoelectric structure for cooling an integrated circuit (IC) chip, the thermoelectric structure comprises a first type superlattice layer formed on top of the IC chip connected to a first voltage, and a second type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being different from the first voltage, wherein an power supply current flows through the first and second type superlattice layer for cooling the IC chip.

Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

Abstract: An integrated circuit chip package and a method of manufacture thereof are provided. In one embodiment, the integrated circuit chip package comprises a semiconductor die having power and ground routings, a plurality of through wafer vias disposed within the semiconductor die, the through wafer vias connected to the power and ground routings, and a substrate attached to the semiconductor die, the substrate having power and ground leads connected to the through wafer vias for transferring power from the substrate to the semiconductor die.

Abstract: A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided over which a spirally patterned conductor layer is formed to produce a planar spiral inductor. A via hole is formed in the substrate within the spirally patterned conductor layer, the via hole being formed by through silicon via (TSV). Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface thereof.

Abstract: A system for processing multimedia data outputs multiple digital data streams of different compressed ratios or types to adapt to multiple limitations of storage spaces and transmission bandwidths, and thus reduce the repetition for processing the digital data streams to save the central processing unit (CPU) resources.

Abstract: A manufacturing method of a color filter substrate is provided. In the method, a substrate is provided. A first color layer, a second color layer, and a third color layer are then sequentially formed on the substrate. At least any two of the first color layer, the second color layer, and the third color layer are partially overlapped to form a number of supporters. Next, a common electrode layer is formed on the substrate to cover the first color layer, the second color layer, the third color layer, and the supporters. A light-shielding layer is then formed on the common electrode layer, and a portion of the light-shielding layer is disposed over the supporters. Based on the manufacturing method of the color filter substrate, fewer masks are required.

Abstract: An integrated circuit chip package and a method of manufacture thereof are provided. In one embodiment, the integrated circuit chip package comprises a semiconductor die having power and ground routings, a plurality of through wafer vias disposed within the semiconductor die, the through wafer vias connected to the power and ground routings, and a substrate attached to the semiconductor die, the substrate having power and ground leads connected to the through wafer vias for transferring power from the substrate to the semiconductor die.

Abstract: A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.

Abstract: A hybrid flip chip and wire bond semiconductor connection package for an integrated circuit. The hybrid package includes a package substrate, a plurality of flip chip pads, and a plurality of wire-bond pads. The package substrate has at least one void or opening with a top side and a bottom side. The flip chip pads mounted on the top side of the package substrate, while the wire-bond pads mounted on the bottom side of the package substrate. The wire-bond pads are configured to receive the integrated circuit.

Abstract: A method and system for integrally checking a chip layout dataset and a package substrate layout dataset for errors are disclosed. The package substrate layout dataset is converted from a first format into a second format in which the chip layout dataset is provided. The chip layout dataset of the second format is combined with the package substrate layout dataset of the second format into a combined dataset. The combined dataset is then checked for errors or design rule violations.

Abstract: A system for processing multimedia data outputs multiple digital data streams of different compressed ratios or types to adapt to multiple limitations of storage spaces and transmission bandwidths, and thus reduce the repetition for processing the digital data streams to save the central processing unit (CPU) resources.

Abstract: A method is disclosed for completing a flip chip package design by re-using mask designs in a tool library. The method comprises analyzing one or more input/out bump locations of a chip, analyzing one or more solder ball locations of a package hosting the chip with regard to a predetermined printed circuit board, and designing the package hosting the chip by using a tool library containing one or more existing mask designs for re-use, wherein when one or more existing mask designs are used for the package, at least one custom connection layer of the package is redesigned when needed for connecting the chip to the printed circuit board without producing a full set of new masks for the package.

Abstract: A method is disclosed for completing a flip chip package design by re-using mask designs in a tool library. The method comprises analyzing one or more input/out bump locations of a chip, analyzing one or more solder ball locations of a package hosting the chip with regard to a predetermined printed circuit board, and designing the package hosting the chip by using a tool library containing one or more existing mask designs for re-use, wherein when one or more existing mask designs are used for the package, at least one custom connection layer of the package is redesigned when needed for connecting the chip to the printed circuit board without producing a full set of new masks for the package.