Patents by Inventor Shih-Cheng Chen

Shih-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984363
    Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial feature having a first semiconductor material over the semiconductor substrate, and a second epitaxial feature having a second semiconductor material over the semiconductor substrate. The second semiconductor material being different from the first semiconductor material. The semiconductor device further includes a first silicide layer on the first epitaxial feature, a second silicide layer on the second epitaxial feature, a metal layer on the first silicide layer, a first contact feature over the metal layer, and a second contact feature over the second silicide layer. A first number of layers between the first contact feature and the first epitaxial feature is greater than a second number of layers between the second contact feature and the second epitaxial feature.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20240154025
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal
    Type: Application
    Filed: January 10, 2024
    Publication date: May 9, 2024
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20240153958
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Application
    Filed: January 7, 2024
    Publication date: May 9, 2024
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240144467
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20240147556
    Abstract: In some examples, a device can include a first antenna having a first wireless connection with a first computing device, a second antenna having a second wireless connection with a second computing device, and a controller to determine a signal strength of the first wireless connection and a signal strength of the second wireless connection, designate, in response to the signal strength of the first wireless connection being greater than a threshold signal strength, the first wireless connection as an active connection and the second wireless connection as a standby connection, and cause the peripheral device to communicate with the first computing device via the active connection of the first antenna while maintaining the second wireless connection to the second computing device via the second antenna, where the second wireless connection remains as the standby connection.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Min-Hsu Chuang, Xin-Chang Chen, Pai-Cheng Huang, Chin-Hung Ma, Shih-Yen Cheng
  • Publication number: 20240136418
    Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng CHEN, Chun-Hsiung LIN, Chih-Hao WANG
  • Patent number: 11967596
    Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 11967594
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11952044
    Abstract: An all-terrain vehicle is provided. The all-terrain vehicle includes a vehicle frame unit. A steering mechanism is rotatably mounted to a front side of the vehicle frame unit. Front wheels are rotatable mounted to a lower side of the steering mechanism as being arranged pairwise as a left-side one and a right-side one and are controllable by the steering mechanism. The all-terrain vehicle includes a vehicle cover unit covering a periphery of the vehicle frame unit. The vehicle cover unit includes a front vehicle cover section. An open receiving space is formed between a top side of the front wheels and the front vehicle cover section. An inertial sensor is arranged in the open receiving space. As such, mounting and servicing the inertial sensor can be carried out without removing the front vehicle cover section or other parts, and thus, mounting and servicing of the inertial sensor is made easy.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: April 9, 2024
    Assignee: KWANG YANG MOTOR CO., LTD.
    Inventors: Te-Feng Chen, Guei-Cheng Ye, Shih-Bin Chien
  • Publication number: 20240104288
    Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Shih-Wei PENG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Shun Li CHEN, Wei-Cheng LIN
  • Patent number: 11940737
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Patent number: 11942750
    Abstract: A laser inspection system is provided. A laser source emits a laser with a first spectrum and the laser is transmitted by a first optical fiber. A gain optical fiber doped with special ions is connected to the first optical fiber, and a light detector is provided around the gain optical fiber. When the laser with the first spectrum passes through the gain optical fiber, the gain optical fiber absorbs part of the energy level of the laser with the first spectrum, so that the laser with the first spectrum is converted to generate light with a second spectrum based on the frequency conversion phenomenon. The light detector detects the intensity of the light with the second spectrum, so that the power of the laser source can be obtained.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: March 26, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Chi Lee, Hsin-Chia Su, Shih-Ting Lin, Yu-Cheng Song, Fu-Shun Ho, Chih-Chun Chen
  • Patent number: 11938405
    Abstract: An electronic device and a method for detecting abnormal device operation are provided. The method includes: obtaining multiple action events of a movable input device, and each action event including a relative coordinate and a time stamp of the movable input device; generating multiple absolute coordinates based on the relative coordinate of each action event; estimating multiple speed vectors based on the absolute coordinates and the time stamp of each action event; estimating multiple acceleration vectors based on the speed vectors and the time stamp of each action event; and estimating a probability of abnormal operation based on the speed vectors and the acceleration vectors.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: March 26, 2024
    Assignee: Acer Incorporated
    Inventors: Tien-Yi Chi, Wei-Chieh Chen, Shih-Cheng Huang, Tzu-Lung Chuang
  • Publication number: 20240096883
    Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu
  • Publication number: 20240096895
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Publication number: 20240097323
    Abstract: In some examples, a device can include an antenna to emit waves in a radiation pattern having a first beamwidth, a directional radiation control device located in a path of the waves, where the directional radiation control device is to receive the waves from the antenna and is shaped to cause the waves to be directed in a different radiation pattern having a second beamwidth that is larger than the first beamwidth.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Chin-Hung Ma, Pai-Cheng Huang, Po Chao Chen, Shih-Huang Wu
  • Publication number: 20240096893
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Publication number: 20240088144
    Abstract: A gate structure includes a metal layer, a barrier layer, and a work function layer. The barrier layer covers a bottom surface and sidewalls of the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure. The work function layer surrounds the barrier layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu
  • Publication number: 20240087356
    Abstract: A display apparatus and an fingerprint sensing method thereof are provided. A display panel of the display apparatus has a pixel circuit array, an in-display touch sensor array, and an in-display fingerprint sensor array. A driving circuit drives the in-display fingerprint sensor array to read a fingerprint image. A current display frame period is divided into a plurality of unit periods, each of the unit periods includes at least one fingerprint sensing period and one or both of a display driving period and a touch sensing period. The driving circuit resets a current fingerprint sensor in the in-display fingerprint sensor array during a first fingerprint sensing period among these fingerprint sensing periods of the first display frame period. The driving circuit reads a sensing result of the current fingerprint sensor during a second fingerprint sensing period succeeding to the first fingerprint sensing period.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Cho-Hsuan Jhang, Chao-Yu Meng, Shih-Cheng Chen, Chih-Peng Hsia
  • Patent number: 11929287
    Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Kuan-Ting Pan, Jung-Hung Chang, Lo-Heng Chang, Chien Ning Yao