Abstract: A method includes: forming a first mask over a substrate; forming first openings and a second opening in the first mask; forming first wells in first regions of the substrate exposed by the first openings and an alignment implant in a second region of the substrate exposed by the second opening; forming an alignment mark by recessing the alignment implant; and patterning a multi-layer semiconductor lattice under alignment of the alignment mark.

Abstract: A method includes forming a photoresist layer over a wafer; aligning a first photomask with a first area of the wafer; performing a first exposure process to a first portion of the photoresist layer within the first area of the wafer; aligning a second photomask with a second area of the wafer, wherein aligning the first photomask and aligning the second photomask are performed using an alignment mark within a stitching zone of the wafer, the stitching zone being an overlapping region of the first area and the second area; performing a second exposure process to a second portion of the photoresist layer within the second area of the wafer; and performing a development process to remove the first and second portions of the photoresist layer.

Abstract: An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

Abstract: An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

Abstract: A method includes: forming a first stack of semiconductor channels and a second stack of semiconductor channels over a substrate, the first stack being adjacent the second stack, a transition region overlapping neighboring protruding corners of the first stack and the second stack; forming a plurality of sacrificial gates over the first stack and the second stack, the plurality of sacrificial gates extending in a first direction and being arranged along a second direction transverse the first direction based on a first pitch along a second direction, each of the plurality of sacrificial gates having a first width; simultaneously with the forming a plurality of sacrificial gates, forming a bar structure over the transition region and adjacent to the plurality of sacrificial gates, the bar structure having a second width that exceeds a sum of the first pitch and the first width; forming a plurality of source/drain openings in areas of the first and second stacks of semiconductor channels that are exposed by the

Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

Abstract: An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

Abstract: An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

Abstract: A method includes forming a first mandrel pattern and a second mandrel pattern. The first mandrel pattern includes at least first and second mandrels for a mandrel-spacer double patterning process. The second mandrel pattern includes at least a third mandrel inserted between the first and second mandrels. The first mandrel pattern and the second mandrel pattern include a same material. The first and second mandrels are merged together with the third mandrel to form a single pattern.

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

Abstract: A method of fabricating a semiconductor device includes generating at least one photomask based on a layout and forming a plurality of active patterns on a substrate, using the at least one photomask. The layout includes a plurality of first patterns that extend parallel to each other in a first direction on a low-density region of the layout and a plurality of second patterns that extend parallel to each other in the first direction on a high-density region of the layout. The forming of the plurality of active patterns includes using the first patterns and the second patterns of the layout to respectively form a plurality of first active patterns and a plurality of second active patterns on the substrate.

Abstract: An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

Abstract: An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.