Patents by Inventor Shih-Chi Fu
Shih-Chi Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170062222Abstract: A method of patterning a substrate includes forming a hard mask layer over the substrate; forming a first material layer over the hard mask layer; and forming a trench in the first material layer. The method further includes treating the hard mask layer with an ion beam through the trench. An etching rate of a treated portion of the hard mask layer reduces with respect to an etching process while an etching rate of untreated portions of the hard mask layer remains substantially unchanged with respect to the etching process. After the treating of the hard mask layer, the method further includes removing the first material layer and removing the untreated portions of the hard mask layer with the etching process, thereby forming a hard mask over the substrate. The method further includes etching the substrate with the hard mask as an etch mask.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Tsung-Lin Yang, Hua Feng Chen, Kuei-Shun Chen, Min-Yann Hsieh, Po-Hsueh Li, Shih-Chi Fu, Yuan-Hsiang Lung, Yan-Tso Tsai
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Publication number: 20170017745Abstract: A method includes receiving an integrated circuit design layout that includes first and second layout blocks separated by a first space. The first and second layout blocks include, respectively, first and second line patterns oriented lengthwise in a first direction. The method further includes adding a dummy pattern to the first space, which connects the first and second line patterns. The method further includes outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format. The mandrel pattern layout includes the first and second line patterns and the dummy pattern. The cut pattern layout includes a pattern corresponding to the first space. In embodiments, the method further includes manufacturing a first mask with the mandrel pattern layout and manufacturing a second mask with the cut pattern layout. In embodiments, the method further includes patterning a substrate with the first mask and the second mask.Type: ApplicationFiled: July 16, 2015Publication date: January 19, 2017Inventors: Chung-Ming Wang, Chih-Hsiung Peng, Chi-Kang Chang, Kuei-Shun Chen, Shih-Chi Fu
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Patent number: 9543161Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a flowable-material (FM) layer over a substrate. The substrate has a first region and a second region. A top surface of the FM layer in the first region is higher than a top surface of the FM layer in the second region. The method also includes forming a plurality of trenches in the FM layer in the first region and performing annealing process to reflow the FM layer, wherein the plurality of trenches are filled with the FM layer.Type: GrantFiled: February 10, 2016Date of Patent: January 10, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Hao Su, Yu-Lun Liu, Chi-Kang Chang, Shih-Chi Fu, Kuei-Shun Chen, Chloe Hsu
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Patent number: 9437650Abstract: A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region.Type: GrantFiled: May 26, 2015Date of Patent: September 6, 2016Assignee: Taiwam Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chen Lu, Ching-Sen Kuo, Shih-Chi Fu, Ming-Ying Hsieh
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Patent number: 9401384Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements, wherein a top portion of the deep doped region is below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with the top portion of the deep doped region.Type: GrantFiled: October 8, 2015Date of Patent: July 26, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi Fu, Kai Tzeng, Wen-Chen Lu
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Publication number: 20160124323Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.Type: ApplicationFiled: May 7, 2015Publication date: May 5, 2016Inventors: Hsueh-Yi CHUNG, Yung-Cheng CHEN, Fei-Gwo TSAI, Chi-Hung LIAO, Shih-Chi FU, Wei-Ti HSU, Jui-Ping CHUANG, Tzong-Sheng CHANG, Kuei-Shun CHEN, Meng-Wei CHEN
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Publication number: 20160027839Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements, wherein a top portion of the deep doped region is below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with the top portion of the deep doped region.Type: ApplicationFiled: October 8, 2015Publication date: January 28, 2016Inventors: Shih-Chi FU, Kai TZENG, Wen-Chen LU
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Publication number: 20160005814Abstract: A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer.Type: ApplicationFiled: September 14, 2015Publication date: January 7, 2016Inventors: Shih-Chi Fu, Chien-Chih Chou
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Patent number: 9171876Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.Type: GrantFiled: May 30, 2014Date of Patent: October 27, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi Fu, Kai Tzeng, Wen-Chen Lu
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Patent number: 9136349Abstract: A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer.Type: GrantFiled: January 6, 2012Date of Patent: September 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chi Fu, Chien-Chih Chou
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Publication number: 20150255503Abstract: A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region.Type: ApplicationFiled: May 26, 2015Publication date: September 10, 2015Inventors: Wen-Chen Lu, Ching-Sen Kuo, Shih-Chi Fu, Ming-Ying Hsieh
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Patent number: 9040341Abstract: A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region.Type: GrantFiled: June 4, 2012Date of Patent: May 26, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chen Lu, Ching-Sen Kuo, Shih-Chi Fu, Ming-Ying Hsieh
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Publication number: 20140264502Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.Type: ApplicationFiled: May 30, 2014Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi FU, Kai TZENG, Wen-Chen LU
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Patent number: 8809172Abstract: Methods of forming self-aligned patterns for performing oppositely doped deep implantations in a semiconductor substrate are disclosed. The semiconductor substrate has implantation and non-implantation regions. The methods include forming a hardmask pattern for a first implantation with a first conductivity-type dopant, depositing an etch stop layer, filling trenches between the hardmask pattern with a sacrificial filler material having a higher wet etch resistance than the hardmask, removing a top portion of the sacrificial filler material and the etch stop layer over a top surface of the hardmask pattern, removing the hardmask pattern in the implantation region by wet etching, and performing a second ion implantation with a second conductivity type dopant opposite of the first conductivity type.Type: GrantFiled: March 15, 2013Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yan Li, Shih-Chi Fu, Ching-Sen Kuo, Wen-Chen Lu
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Patent number: 8771534Abstract: Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.Type: GrantFiled: January 13, 2012Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Chang Chen, Shih-Chi Fu, Wang-Pen Mo, Hung-Chang Hsieh
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Patent number: 8766406Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.Type: GrantFiled: January 8, 2013Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chi Fu, Kai Tzeng, Wen-Chen Lu
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Patent number: 8710560Abstract: A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer.Type: GrantFiled: August 8, 2007Date of Patent: April 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Chih Hsieh, Shih-Chang Liu, Shih-Chi Fu, Tzu-Hsuan Hsu, Chung-Yi Yu, Gwo-Yuh Shiau, Chia-Shiung Tsai
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Patent number: 8692296Abstract: Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.Type: GrantFiled: February 9, 2012Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chang Chen, Shun-Shing Yang, Shih-Chi Fu, Wang-Pen Mo, Hung-Chang Hsieh
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Patent number: 8623229Abstract: Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.Type: GrantFiled: November 29, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Chang Chen, Shih-Chi Fu, Wang-Pen Mo, Hung Chang Hsieh
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Publication number: 20130323876Abstract: A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region.Type: ApplicationFiled: June 4, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chen Lu, Ching-Sen Kuo, Shih-Chi Fu, Ming-Ying Hsieh