Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: A charged particle multi-beam lithography system includes an illumination sub-system that is configured to generate a charged particle beam; and multiple plates with a first aperture through the plates. The plates and the first aperture are configured to form a charged particle doublet. The system further includes a blanker having a second aperture whose footprint is smaller than that of the first aperture. The charged particle doublet is configured to demagnify a portion of the charged particle beam passing through the first aperture, thereby producing a demagnified beamlet. The blanker is configured to receive the demagnified beamlet from the charged particle doublet, and is further configured to conditionally allow the demagnified beamlet to travel along a desired path.

Abstract: A charged particle multi-beam lithography system includes an illumination sub-system that is configured to generate a charged particle beam; and multiple plates with a first aperture through the plates. The plates and the first aperture are configured to form a charged particle doublet. The system further includes a blanker having a second aperture whose footprint is smaller than that of the first aperture. The charged particle doublet is configured to demagnify a portion of the charged particle beam passing through the first aperture, thereby producing a demagnified beamlet. The blanker is configured to receive the demagnified beamlet from the charged particle doublet, and is further configured to conditionally allow the demagnified beamlet to travel along a desired path.

Abstract: An apparatus for use in a charged particle multi-beam lithography system is disclosed. The apparatus includes a plurality of charged particle doublets each having a first aperture and each configured to demagnify a beamlet incident upon the first aperture thereby producing a demagnified beamlet. The apparatus further includes a plurality of charged particle lenses each associated with one of the charged particle doublets, each having a second aperture, and each configured to receive the demagnified beamlet from the associated charged particle doublet and to realize one of two states: a switched-on state, wherein the demagnified beamlet is allowed to travel along a desired path, and a switched-off state, wherein the demagnified beamlet is prevented from traveling along the desired path. In embodiments, the first aperture is greater than the second aperture, thereby improving particle beam efficiency in the charged particle multi-beam lithography system.

Abstract: An apparatus for use in a charged particle multi-beam lithography system is disclosed. The apparatus includes a plurality of charged particle doublets each having a first aperture and each configured to demagnify a beamlet incident upon the first aperture thereby producing a demagnified beamlet. The apparatus further includes a plurality of charged particle lenses each associated with one of the charged particle doublets, each having a second aperture, and each configured to receive the demagnified beamlet from the associated charged particle doublet and to realize one of two states: a switched-on state, wherein the demagnified beamlet is allowed to travel along a desired path, and a switched-off state, wherein the demagnified beamlet is prevented from traveling along the desired path. In embodiments, the first aperture is greater than the second aperture, thereby improving particle beam efficiency in the charged particle multi-beam lithography system.

Abstract: The present disclosure provides a method of increasing the wafer throughput by an electron beam lithography system. The method includes scanning a wafer using the maximum scan slit width (MSSW) of the electron beam writer. By constraining the integrated circuit (IC) field size to allow the MSSW to cover a complete field, the MSSW is applied to decrease the scan lanes of a wafer and thereby increase the throughput. When scanning the wafer with the MSSW, the next scan lane data can be rearranged and loaded into a memory buffer. Thus, once one scan lane is finished, the next scan lane data in the memory buffer is read for scanning.

Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

Abstract: The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

Abstract: The present disclosure describes an apparatus of leveling a substrate in a charged particle lithography system. In an example, the apparatus includes a cantilever-based sensor that includes an optical sensor and a cantilever structure. The optical sensor determines a distance between the optical sensor and a surface of the substrate based on light reflected from the cantilever structure. In an example, a first distance is between the cantilever structure and optical sensor, a second distance is a height of the cantilever structure, and a third distance is between the optical sensor and the surface of the substrate. The optical sensor determines the first distance based on the light reflected from the cantilever structure, such that the third distance is determined from the first distance and the second distance.

Abstract: The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

Abstract: The present disclosure provides a method of increasing the wafer throughput by an electron beam lithography system. The method includes scanning a wafer using the maximum scan slit width (MSSW) of the electron beam writer. By constraining the integrated circuit (IC) field size to allow the MSSW to cover a complete field, the MSSW is applied to decrease the scan lanes of a wafer and thereby increase the throughput. When scanning the wafer with the MSSW, the next scan lane data can be rearranged and loaded into a memory buffer. Thus, once one scan lane is finished, the next scan lane data in the memory buffer is read for scanning.