Abstract: Provided is a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying.

Abstract: The present disclosure describes an apparatus of leveling a substrate in a charged particle lithography system. In an example, the apparatus includes a cantilever-based sensor that includes an optical sensor and a cantilever structure. The optical sensor determines a distance between the optical sensor and a surface of the substrate based on light reflected from the cantilever structure. In an example, a first distance is between the cantilever structure and optical sensor, a second distance is a height of the cantilever structure, and a third distance is between the optical sensor and the surface of the substrate. The optical sensor determines the first distance based on the light reflected from the cantilever structure, such that the third distance is determined from the first distance and the second distance.

Abstract: The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

Abstract: The present disclosure involves a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour.

Abstract: A file-converting method is disclosed. The file-converting method includes the following steps. Obtain an architecture file from Mechanical Computer-aided Design (MCAD) software. Analyze the architecture file to obtain at least an architecture element, which is not compatible with Electrical Computer-aided Design (ECAD) software, according to a converting database. Replace the architecture element in the architecture file with a symbol element, which is compatible with the ECAD software, to generate a layout file.