Abstract: The present disclosure teaches a system and method for register-transfer level (RTL) design checking for exploring mismatches and ambiguous language semantics that occur during the simulation and synthesis phases of the circuit design. In particular, the present disclosure utilizes identified patterns of design violations that occur as a result of these mismatches to create rule objects. The rule objects are then used to identify circuit design violations relating to mismatches between designer intent and ambiguous language. The rule objects are also categorized into different categories so as aid in the analysis of design rule violations and to identify the major impacts to the design qualities and to provide a confidence level of the overall design quality.

Abstract: This invention proposes a multi-bit resistive-switching memory cell and array thereof. Multiple conduction paths are formed on each memory cell and independent of each other, and each conduction path can be in a high-resistance or low-resistance state, so as to form a multi-bit resistive-switching memory cell. A memory cell array can be formed by arranging a plurality of multi-bit resistive-switching memory cells, and the memory cell array provides a simple, high density, high performance and cost-efficient proposal.

Abstract: This invention proposes a multi-bit resistive-switching memory cell and array thereof. Multiple conduction paths are formed on each memory cell and independent of each other, and each conduction path can be in a high-resistance or low-resistance state, so as to form a multi-bit resistive-switching memory cell. A memory cell array can be formed by arranging a plurality of multi-bit resistive-switching memory cells, and the memory cell array provides a simple, high density, high performance and cost-efficient proposal.

Abstract: A method for verifying a circuit design includes a step of assigning numerical values 1/ai to input ports of the circuit design according to a function ai+1=(ai?1)2+1, wherein i represents the number of the input port and the numerical value a1 is not equal to 2 or 1. Preferably, a1 is equal to or larger than 3, and is a positive integer. Particularly, the numerical value represents l's probability. In addition, the present method further includes a step of calculating an output value at an output port of the circuit design based on the numerical values assigned to the input port, and calculating the output value is performed from the input port to the output port at a Boolean gate level.

Abstract: A method for verifying a circuit design comprises a step of assigning numerical values 1/ai to input ports of the circuit design according to a function ai+1=(ai?1)2+1, wherein represents the number of the input port and the numerical value a1 is not equal to 2 or 1. Preferably, a1 is equal to or larger than 3, and is a positive integer. Particularly, the numerical value represents 1's probability. In addition, the present method further comprises a step of calculating an output value at an output port of the circuit design based on the numerical values assigned to the input port, and calculating the output value is performed from the input port to the output port at a Boolean gate level.