Abstract: A compound for treating a protein kinase-related disease or disorder having a structure of formula (I) wherein G is a heteroaryl, heterocyclic or alkyne; X is N or CH; L1 is —N(R7)—, —O—, —C(S)—, —C(O)—, or —S—; L2 is —N(R8)— or —O—; R1 and R2 are independently hydrogen, halogen, hydroxyl, amino, cyano, nitro, carboxy, C1-C4 alkoxy, C1-C4 alkoxy C1-C4 alkoxy, N,N—(C1-C4 dialkyl)amino C1-C4 alkoxy, N—(C1-C4 alkyl)amino C1-C4 alkoxy, C1-C4 alkanoyl, C1-C4 alkanoyloxy, N—(C1-C4 alkyl)amino, N,N—(C1-C4 dialkyl)amino, C1-C4 alkanoyl amino, or heterocyclyl, wherein C1-C4 alkyl is optionally substituted with one or more substituents selected from fluorine and chlorine; R3, R4 and R5 are independently hydrogen, fluorine or chlorine; R6 is C1-C4 alkyl or aryl, which is optionally substituted with one or more substituents selected from halogen, hydroxyl, amino, cyano, nitro; or R6 and R8 form a 5-6 membered cyclyl or heterocyclyl.

Abstract: A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition.

Abstract: A signal processing apparatus includes: a signal conversion circuit, for performing a signal conversion operation on a reception signal to generate a first output signal according to a first clock signal, and performing the signal conversion operation on the reception signal according to a second clock signal to generate a second output signal; an amplitude adjustment circuit, coupled to the signal conversion circuit, for calculating an amplitude value of the reception signal according to the first output signal, and accordingly adjusting an amplitude of the reception signal; and a phase adjustment circuit, for adjusting a phase of the second clock signal according to the second output signal.

Abstract: A filtering system includes a first filtering module, which includes a first frequency translating device and a first filter. The first frequency translating device includes a center frequency control end that receives a first control signal and an input end that receives an input signal, and performs a first frequency translation on the input signal by utilizing a first control frequency of the first control signal as a center frequency. The first filter performs a first filter on the input signal according to equivalent impedance of a circuit coupled to the input end, and generates in collaboration with the first frequency translating device a first filtered input signal at an output end of the filtering system. The equivalent impedance determines a bandwidth of the first filtered input signal.

Abstract: A filtering system includes a first filtering module, which includes a first frequency translating device and a first filter. The first frequency translating device includes a center frequency control end that receives a first control signal and an input end that receives an input signal, and performs a first frequency translation on the input signal by utilizing a first control frequency of the first control signal as a center frequency. The first filter performs a first filter on the input signal according to equivalent impedance of a circuit coupled to the input end, and generates in collaboration with the first frequency translating device a first filtered input signal at an output end of the filtering system. The equivalent impedance determines a bandwidth of the first filtered input signal.

Abstract: A communication device is provided in the present invention. The communication device comprises an oscillation signal source, a tunable capacitor array, a frame counter; and a control module. The control module is configured to jointly or separately control the tunable capacitor array and the frame counter to compensate a first frequency offset of the oscillation signal source when the communication device operates in a first mode, and to jointly or separately control the tunable capacitor array and the frame counter to compensate a second frequency offset of the oscillation signal source when the communication device operates in a second mode.

Abstract: A signal processing system includes a module under test, an oscillation signal generator, a translational filter, and a testing module. The module under test has a signal input end. The oscillation signal generator generates an oscillation signal. The translational filter includes a mixer controlled by the oscillation signals. The mixer has a high-frequency side and a low-frequency side. The high-frequency side is coupled to the signal input end of the module under test. The testing module is coupled to the low-frequency side of the mixer. When the signal processing system is in a testing mode, the testing module provides a testing signal to the low-frequency side, so as to generate a high-frequency testing signal at the high-frequency side of the mixer.

Abstract: A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition.

Abstract: A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal.

Abstract: A circuit, including a receiving path, for converting a first analog radio frequency (RF) input signal to a digital intermediate frequency (IF) input signal, wherein the first analog RF input signal includes a first signal component conforming to a first wireless transmission standard and a second signal component conforming to a second wireless transmission standard; a first digital down converter, for receiving and processing the digital IF input signal to generate a first digital baseband signal corresponding to the first signal component; a second digital down converter, for receiving and processing the digital IF input signal in order to generate a second digital baseband signal corresponding to the second signal component; a first baseband processing module, for processing the first digital baseband signal according to the first wireless transmission standard; and a second baseband processing module, for processing the second digital baseband signal according to the second wireless transmission standard

Abstract: A transceiver in-phase and quadrature (IQ) calibration method is provided. When calibrating the transceiver, an adjusting unit is connected to an output terminal of a transmitter to receive a first radio-frequency (RF) signal. The adjusting unit adjusts a phase delay of the first RF signal to generate a second RF signal to be inputted to an input terminal of a receiver. Through adjusting the phase delay of the first RF signal, both the transmitter and the receiver can be calibrated at the same time.

Abstract: A clock generating circuit includes a phase detector for detecting a phase difference between a first clock and a second clock to generate a detecting result associated with the phase difference, a first filtering device for filtering the detecting result, a charge pump for generating a control signal according to the filtered detecting result, a second filtering device for filtering the control signal, and a controllable oscillator for generating an output clock according to the filtered control signal, wherein the output clock is utilized to generate the second clock.

Abstract: A direct conversion receiver including a mixer, a measuring module and a calibration module is provided. When the calibration module adjusts the switch duty cycle of the mixer to being shorter than a standard duty cycle, a first second-order inter-modulation distortion is measured. When the calibration module adjusts the switch duty cycle to being longer than the standard duty cycle, a second second-order inter-modulation distortion is measured. According to the measured distortions, the calibration module determines a calibration signal and provides the calibration signal to the mixer, so as to allow the mixer to have a calibrated duty cycle.

Abstract: A signal processing apparatus includes: a signal conversion circuit, for performing a signal conversion operation on a reception signal to generate a first output signal according to a first clock signal, and performing the signal conversion operation on the reception signal according to a second clock signal to generate a second output signal; an amplitude adjustment circuit, coupled to the signal conversion circuit, for calculating an amplitude value of the reception signal according to the first output signal, and accordingly adjusting an amplitude of the reception signal; and a phase adjustment circuit, for adjusting a phase of the second clock signal according to the second output signal.

Abstract: An offset phase-locked loop (PLL) transmitter comprises a clock generator that generates a first clock signal; a detector that detects a phase difference between an input data signal and a feedback data signal to generate a control signal; a controlled oscillator, coupled to the detector, that generates an output data signal according to the control signal; a mixer, coupled to the controlled oscillator and the clock generator, that mixes the output data signal according to the first clock signal to generate the feedback data signal; and a control circuit, coupled to the detector and the controlled oscillator, that adjusts the operating frequency curve of the controlled oscillator by one of a first step distance and a second step distance smaller than the first step distance such that the control signal is substantially equal to a predetermined value.

Abstract: A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal.

Abstract: The invention discloses an apparatus and method for measuring a blood pressure. In particular, the method and apparatus according to the invention are capable of eliminating motion artifacts induced by, for example, talking, irregular breathing, frequent swallowing, coughing, shaking, and so on motions of a subject. The method and apparatus according to the invention utilizes a set of fuzzy logic rules and a curve-fitting way to eliminate the motion artifacts.

Abstract: A voltage-controlled oscillator (VCO) control circuit, used for controlling a VCO to process phase locking procedure after receiving a frequency locking signal, comprises an operating frequency controller and a judgment unit. The operating frequency controller, coupled to the VCO and the judgment unit, generates one of a first control code and a second control code to the VCO. The judgment unit, coupled to an input end of the VCO, generates a phase locking signal according to a voltage control signal inputted to the VCO. When the operating frequency controller receives the frequency locking signal, the operating frequency controller generates a first control code to control the VCO to switch from a first candidate VCO curve to a second candidate VCO curve. When the operating frequency controller receives the phase locking signal, the operating frequency controller generates a second control code to control the VCO to switch from the second candidate VCO curve to the first candidate VCO curve.

Abstract: A 3D image capturing device includes a first lens module, a second lens module, a single sensor, an image sensor; a cross dichroic prism; a first mirror; and a second mirror. The first and second lens module have a first optical axis and a second optical axis, respectively. The second lens module is located juxtaposed with the first lens module. The second optical axis is parallel with the first optical axis. The first and second mirrors are arranged at opposite sides of the cross dichroic prism. The first and second mirrors are configured for reflecting and directing light beams from the first and second lens modules to the cross dichroic prism. The cross dichroic prism is configured to redirect the reflected light beams from the first and second mirrors to the image sensor.

Abstract: An electronic device includes a main body and an image capturing device positioned on the main body. The image capturing device includes a fixing pole, a rotating plate, two lens modules, and an image sensor. The fixing pole is fixed on the main body. The rotating plate is sleeved over the fixing pole and rotates around the fixing pole. The two lens modules are mounted on the rotating plate and symmetrical with the fixing pole. The image sensor is arranged on the main body. The rotating plate is rotated to make the two lens modules be alternated to align with the image sensor.