Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: A method for performing automatic activation control regarding VRS and associated apparatus are provided. The method applicable to a processing circuit may include: utilizing a rendering classifier to intercept at least one set of original graphic commands on a command path to obtain at least one rendering property, for classifying rendering corresponding to the at least one set of original graphic commands; utilizing the rendering classifier to classify the rendering into at least one predetermined rendering type among multiple predetermined rendering types according to the at least one rendering property, in order to determine at least one shading rate corresponding to the at least one predetermined rendering type for the rendering; and utilizing a shading rate controller to control the processing circuit to selectively activate a VRS function of the processing circuit, for rendering at the at least one shading rate corresponding to the at least one predetermined rendering type.

Abstract: A computing system with graphics processor boosting is shown. The computing system has a graphics processing unit controlling a display, a code memory storing instructions, and a processor operating the graphics processing unit to control the display. The processor is configured to execute the instructions retrieved from the code memory to implement a plurality of graphics processor boosting modules for the graphics processing unit, and implement an activation controller that controls activation of the different graphics processor boosting modules through different configuration interfaces with balances between the different graphics processor boosting modules.

Abstract: A system, method, and computer program product are provided for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor die, a lid, a liquid metal, a gel and a thermal dissipation structure. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate and covers the semiconductor die. The lid has an opening to expose the semiconductor die. The liquid metal is disposed on the semiconductor die. The gel is disposed between the semiconductor die and the lid. The thermal dissipation structure is disposed on the lid and covers the opening. The semiconductor die, the gel and the thermal dissipation structure form a closed space for accommodating the liquid metal.

Abstract: Disclosed is a light-emitting array structure having a substrate, a plurality of light-emitting pixel units, a plurality of first and second signal wires, and an encapsulating layer. The light-emitting pixel units are arranged in array on the substrate. Each light-emitting pixel unit includes a driving chip, a first flat layer, a first redistribution layer, a second flat layer, a second redistribution layer, and a light-emitting diode. Each first signal wire is electrically connected to a corresponding one of the first redistribution layers and extends in a first direction. The second signal wires extend in a level different from the first signal wires. Each second signal wire is electrically connected to a corresponding one of the second redistribution layers and extends in a second direction different from the first direction. The encapsulating layer covers the light-emitting pixel units, the first and second signal wires, and the substrate.

Abstract: An IC structure includes first and second complementary field-effect transistors (CFETs) positioned in a semiconductor wafer, each of the first and second CFETs including a gate structure extending in a first direction, an n-type channel extending through the gate structure in a second direction perpendicular to the first direction, and a p-type channel extending through the gate structure in the second direction and aligned with the n-type channel in a third direction perpendicular to each of the first and second directions. A metal line extends in the first direction, is aligned with each of the first and second CFETs in the third direction, and is configured to distribute a power supply or reference voltage to each of the first and second CFETs. The metal line is a metal line closest to each of the first and second CFETs along the third direction and extending in the first direction.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: A semiconductor package structure includes a first component, a bonding structure on the first component, a second component connected to the first component, and a copper connector on the second component. The bonding structure includes a copper base on the first component and copper protruding portions on the copper base. The second component is connected to the first component by bonding the copper protruding portions to the copper connector, and the copper protruding portions are in contact with the copper connector.

Abstract: There is provided a moving robot including a first light source module and a second light source module respectively project a first light section and a second light section, which are vertical light sections, in front of a moving direction, wherein the first light section and the second light section cross with each other at a predetermined distance in front of the moving robot so as to eliminate a detection dead zone between the first light source module and the second light source module in front of the moving robot to avoid collision with an object during operation.

Abstract: A key structure includes a baseplate, a keycap and a connecting assembly. The keycap includes a plurality of first pivot portions and a plurality of sliding slots. The connecting assembly includes a first outer frame, two first inner frames, a second outer frame and a second inner frame. The first inner frames are disposed in two accommodating portions of the first outer frame. Two sides of the first outer frame are respectively connected to part of the sliding slots and the baseplate. Two sides of the first inner frame are respectively connected to the first pivot portion and the base plate. Two sides of the second outer frame are respectively connected to part of the sliding slots and the fixing side. Two sides of the second inner frame are respectively pivoted to one of the first inner frames and the base plate.

Abstract: A semiconductor device includes a bottom package, a top package stacked on the bottom package, and an interposer disposed between the bottom package and the top package. The top package is electrically connected to the interposer through a plurality of peripheral solder balls. At least a dummy thermal feature is disposed on the interposer and surrounded by the plurality of peripheral solder balls.

Abstract: There is provided a moving robot including a first light source module and a second light source module respectively project a first light section and a second light section, which are vertical light sections, in front of a moving direction, wherein the first light section and the second light section cross with each other at a predetermined distance in front of the moving robot so as to eliminate a detection dead zone between the first light source module and the second light source module in front of the moving robot to avoid collision with an object during operation.

Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.

Abstract: A semiconductor device is provided. The semiconductor device includes a carrier, an electronic component, an adapter, a first metal wire and a second metal wire. The electronic component is disposed on the carrier. The adapter is disposed on the carrier. The first metal wire connects the electronic component and the adapter. The second metal wire connects the adapter and the carrier.

Abstract: Disclosed herein are system, method, and computer program product embodiments for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.

Abstract: A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.

Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

Abstract: A package-on-package includes a first package and a second package on the first package. The first package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and an IC device are mounted on the bottom substrate in a side-by-side configuration. The logic die has a thickness not less than 125 micrometer. Copper cored solder balls are disposed between around the logic die and the IC device to electrically connect the bottom substrate with the top substrate. A sealing resin is filled into the gap between the bottom substrate and the top substrate and seals the logic die, the IC device, and the copper cored solder balls in the gap.