Patents by Inventor Shih-Chin Lin

Shih-Chin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210174473
    Abstract: Aspects of the disclosure provide a device for processing frames with aliasing artifacts. For example, the device can include a motion estimation circuit, a warping circuit coupled to the motion estimation circuit, and a temporal decision circuit coupled to the warping circuit. The motion estimation circuit can estimate a motion value between a current frame and a previous frame. The warping circuit can warp the previous frame based on the motion value such that the warped previous frame is aligned with the current frame and determine whether the current frame and the warped previous frame are consistent. The temporal decision circuit can generate an output frame, the output frame including either the current frame and the warped previous frame when the current frame and the warped previous frame are consistent, or the current frame when the current frame and the warped previous frame are not consistent.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 10, 2021
    Applicant: MEDIATEK INC.
    Inventors: Jen Cheng LUNG, Pei-Kuei TSUNG, Chih-Wei CHEN, Yao-Sheng WANG, Shih-Che CHEN, Yu-Sheng LIN, Chih-Wen GOO, Shih-Chin LIN, Huang TSUNG-SHIAN, Ying-Chieh CHEN
  • Publication number: 20210132104
    Abstract: A visualization device for a flow field includes a chamber, a power supply, at least one pair of electrodes, and at least one flow field observation module. The flow field observation module includes a high-speed camera, a light detecting component, and a light filter component. The power supply outputs a voltage to generate a plasma, and the pair of electrodes is disposed in the chamber. The flow field observation module is disposed outside the chamber and captures an image of a fluid particle excited by the plasma toward the chamber. The light filter component is disposed between the high-speed camera and the chamber. The light detecting component obtains a light information within the chamber and sends the light information to the light filter component.
    Type: Application
    Filed: December 2, 2019
    Publication date: May 6, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Yung Huang, Yao-Hsien Liu, Kuan-Chou Chen, Yi-Jiun Lin, Shih-Chin Lin, Ching-Chiun Wang
  • Publication number: 20200312732
    Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 1, 2020
    Inventors: Yen-Yao CHI, Nai-Wei LIU, Ta-Jen YU, Tzu-Hung LIN, Wen-Sung HSU, Shih-Chin LIN
  • Publication number: 20200241550
    Abstract: There is provided a cleaning robot including a first light source module and a second light source module respectively project a first light section and a second light section, which are vertical light sections, in front of a moving direction, wherein the first light section and the second light section cross with each other at a predetermined distance in front of the cleaning robot so as to eliminate a detection dead zone between the first light source module and the second light source module in front of the cleaning robot to avoid collision with an object during operation.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Inventors: Shih-Chin LIN, Wei-Chung WANG, Guo-Zhen WANG
  • Publication number: 20200154555
    Abstract: A flow field visualization device includes a chamber, a power supply, at least one pair of electrodes, and at least two high-speed cameras. The power supply outputs a voltage for plasma generation, and the pair of electrodes is disposed in the chamber. The pair of electrodes includes a first electrode and a second electrode. The first electrode has a plurality of first tips, the second electrode has a plurality of second tips, and the first tips and the second tips are aligned with each other. The pair of electrodes generates a periodically densely distributed plasma by exciting a gas in the chamber through the voltage from the power supply. The high-speed cameras are disposed outside the chamber and are positioned in different directions corresponding to the pair of electrodes in order to capture images of different dimensions.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 14, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Yung Huang, Kuan-Chou Chen, Shih-Chin Lin, Yi-Jiun Lin, Ching-Chiun Wang
  • Patent number: 10354974
    Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 16, 2019
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Andrew C. Chang, Tao Cheng
  • Patent number: 10312222
    Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 4, 2019
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng
  • Patent number: 10242927
    Abstract: A semiconductor package includes a substrate, a first electronic component, a film and a package body. The first electronic component is disposed on the substrate and has an upper surface. The film is disposed on the upper surface of the first electronic component. The package body encapsulates the first electronic component and the film.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: March 26, 2019
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Ming-Jen Hsiung
  • Patent number: 10186488
    Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: January 22, 2019
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang
  • Patent number: 10121222
    Abstract: A graphics processing unit (GPU) renders graphical objects into a group of pixels and stores the pixels in an on-chip buffer on the same chip as the GPU. Each pixel has an alpha value that indicates transparency of the pixel. The GPU reads the alpha value of each pixel from the on-chip buffer. According to alpha values of the group of pixels, the GPU generates an alpha hint in the system memory for the group of pixels. The alpha hint represents an aggregate of the alpha values of the group of pixels. The GPU then stores the group of pixels into a frame buffer in the system memory.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: November 6, 2018
    Assignee: MediaTek Inc.
    Inventors: Ying-Chieh Chen, I-Hsuan Lu, Shih-Chin Lin
  • Patent number: 10027330
    Abstract: An arbitrating circuit includes a first NOR gate, a second NOR gate, four resistors and a pull-up circuit. The first transistor is connected with the first node and the second node, and generates a first acknowledging signal. The second transistor is connected with a supply voltage, the second node and the first transistor. The third transistor is connected with the first node and second node, and generates a second acknowledging signal. The fourth transistor is connected with the supply voltage, the first node and the third transistor. The pull-up circuit is connected with the first node, the second node, the first NOR gate and the second NOR gate. If both of the first request signal and the second request signal have a low logic level, a voltage at the second node is pulled up to a high logic level by the pull-up circuit.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: July 17, 2018
    Assignee: Faraday Technology Corp.
    Inventors: Zhao-Yong Zhang, Shih-Chin Lin, Wei-Chang Wang
  • Publication number: 20180169606
    Abstract: An apparatus for producing an inorganic powder and an apparatus for producing and classifying an inorganic powder are provided, wherein the apparatus for producing an inorganic powder includes an insulating tube, at least one pair of annular RF electrodes, and a gas supply apparatus. The pair of annular RF electrodes surrounds the outer circumference of the insulating tube to generate a first electric field region outside the insulating tube and generate a second electric field region having a plasma torch in the insulating tube after being turned on. The gas supply apparatus supplies a reaction mist and an inert gas into the insulating tube to thermally degrade and oxidize the reaction mist into an inorganic powder via the plasma torch.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 21, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Chun-An Lu, Yuan-Ling Tsai, Chiung-Hsiung Chen, Yi-Chen Wu, Shih-Chin Lin
  • Publication number: 20180174359
    Abstract: A graphics system provides frame difference generator hardware for dynamically adjusting a frame rate. The graphics system includes a graphics processing unit (GPU), which generates frames containing tiles of graphics data. The frame difference generator hardware receives the graphics data of a tile of a current frame from the GPU, in parallel with a frame buffer that also receives the graphics data. The frame difference generator hardware computes a difference value between a first value computed from the graphics data and a second value representing a corresponding tile of a previous frame, and accumulates difference values computed from multiple tiles of the current frame and the previous frame to obtain an accumulated value. The accumulated value is reported to software executed by the graphics system for determination of an adjustment to the frame rate.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventors: Ying-Chieh Chen, Shih-Chin Lin, Chih-Yu Chang
  • Publication number: 20180119273
    Abstract: The disclosure is an evaporation apparatus and a method of evaporation using the same. The evaporation apparatus includes an evaporation chamber, an evaporation source, a carrying device, and a fluid disturbance device. The evaporation chamber has an evaporation space, the evaporation source is disposed at a lower part in the evaporation space, and the evaporation source is suitable for accommodating an evaporation source material. The carrying device is disposed to be rotatable about a reference axis as the center at an upper part in the evaporation space and is opposite to the evaporation source; the carrying device is suitable for carrying a substrate and positions the substrate between the evaporation source and the carrying device. The fluid disturbance device is suitable for injecting a disturbed fluid towards the carrying device in the evaporation space.
    Type: Application
    Filed: December 20, 2016
    Publication date: May 3, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Yung Huang, Shih-Chin Lin, Ching-Chiun Wang
  • Publication number: 20180114779
    Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.
    Type: Application
    Filed: December 20, 2017
    Publication date: April 26, 2018
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng
  • Patent number: 9908203
    Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 6, 2018
    Assignee: MEDIATEK INC.
    Inventors: Tao Cheng, Wen-Sung Hsu, Shih-Chin Lin
  • Patent number: 9905562
    Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: February 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry Che Jen Hu, Ming-Jui Chen, Chen-Hsien Hsu
  • Patent number: 9881902
    Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 30, 2018
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng
  • Publication number: 20170338183
    Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang
  • Patent number: 9761534
    Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: September 12, 2017
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang