Abstract: The storage device that includes a non-volatile memory with a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops. The programming loops include applying a programming pulse to a selected word line of the plurality of word lines. The programming loops also include applying a verify pulse VN to the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells that have been programmed to a data state N?1. The data state N?1 has a lower voltage threshold than the data state N.

Abstract: The disclosure provides an error detection method for a memory device, wherein the memory device comprises a plurality of memory blocks, and each of the memory blocks has a plurality of word lines connected to a plurality of memory cells, the error detection method comprises the following steps. Performing a plurality of times of programming operations on the memory cells connected to each of the word lines to program the memory cells as a plurality of programming-level states. Performing a plurality of times of verifying operations on the memory cells to verify the programming-level states respectively. When the number of verifications of the verifying operations for one of the programming-level states is greater than an upper limit number corresponding to the one of the programming-level states, marking the word line as an error word line.

Abstract: The disclosure provides an error detection method for a memory device, wherein the memory device comprises a plurality of memory blocks, and each of the memory blocks has a plurality of word lines connected to a plurality of memory cells, the error detection method comprises the following steps. Performing a plurality of times of programming operations on the memory cells connected to each of the word lines to program the memory cells as a plurality of programming-level states. Performing a plurality of times of verifying operations on the memory cells to verify the programming-level states respectively. When the number of verifications of the verifying operations for one of the programming-level states is greater than an upper limit number corresponding to the one of the programming-level states, marking the word line as an error word line.

Abstract: A method for operating non-volatile storage disclosed herein. The method comprises performing an operation on a set of non-volatile storage elements. The operation on the set of non-volatile storage elements includes providing temperature compensation based on an operation temperature of the set of non-volatile storage elements. The providing temperature compensation includes determining if the operation temperature is outside a temperature range where constant compensation is valid and applying the temperature compensation based on the determination.

Abstract: The storage device that includes a non-volatile memory with a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops. The programming loops include applying a programming pulse to a selected word line of the plurality of word lines. The programming loops also include applying a verify pulse VN to the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells that have been programmed to a data state N?1. The data state N?1 has a lower voltage threshold than the data state N.

Abstract: For a non-volatile memory die formed of multiple blocks of memory cells, the memory die has a multi-bit bad block flag for each block stored on the memory die, such as in a fuse ROM. For each block, the multi-bit flag indicates if the block has few defects and is of the highest reliability category, is too defective to be used, or is in of one of multiple recoverability categories. The multi-bit bad blocks values can be determined as part a test process on fresh devices, where the test of a block can be fail stop for critical category errors, but, for recoverable categories, the test continues and tracks the test results to determine a recoverability category for the block and write this onto the die as a bad block flag for each block. These recoverability categories can be incorporated into wear leveling operations.

Abstract: A method for operating non-volatile storage disclosed herein. The method comprises performing an operation on a set of non-volatile storage elements. The operation on the set of non-volatile storage elements includes providing temperature compensation based on an operation temperature of the set of non-volatile storage elements. The providing temperature compensation includes determining if the operation temperature is outside a temperature range where constant compensation is valid and applying the temperature compensation based on the determination.

Abstract: For a non-volatile memory die formed of multiple blocks of memory cells, the memory die has a multi-bit bad block flag for each block stored on the memory die, such as in a fuse ROM. For each block, the multi-bit flag indicates if the block has few defects and is of the highest reliability category, is too defective to be used, or is in of one of multiple recoverability categories. The multi-bit bad blocks values can be determined as part a test process on fresh devices, where the test of a block can be fail stop for critical category errors, but, for recoverable categories, the test continues and tracks the test results to determine a recoverability category for the block and write this onto the die as a bad block flag for each block. These recoverability categories can be incorporated into wear leveling operations.

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.

Abstract: An X-ray imaging method including the following steps is provided. An X-ray source is provided, wherein the X-ray source includes a housing, a cathode, and an anode target. The housing has an end window. The cathode is disposed in the housing, and the anode target is disposed beside the end window. The cathode is caused to provide an electron beam. A portion of the electron beam hits at least a part of areas of the anode target to generate an X-ray and the X-ray is emitted out of the housing through the end window. The X-ray is caused to irradiate an object to generate X-ray image information. An image detector is used to receive the X-ray image information.

Abstract: A self bonding floor tile includes a main body and a self bonding layer connected with the main body. The self bonding layer includes an absorptive element, a first adhesive and a second adhesive. The first adhesive connects the main body with the self bonding layer. The absorptive element includes a plurality of fibers which are implanted into the first adhesive by flocking process with at least a portion of the absorptive element extending into the first adhesive, and at least a portion of the second adhesive penetrates into the other portion of the absorptive element for connecting the self bonding layer with a support body going to be decorated. The present self bonding floor tile can be quickly installed, easily and partly replaced with low installation and replacement cost.

Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.

Abstract: A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.

Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The one or more control circuits are configured to apply a reference voltage to the memory cells. While applying the reference voltage to the plurality of memory cells, the one or more control circuits are configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to different bit lines connected to the different memory cells.

Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.

Abstract: A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.

Abstract: Reducing peak current and/or power consumption during erase verify of a non-volatile memory is disclosed. During an erase verify, memory cells are verified at a strict reference level that is deeper (e.g., lower threshold voltage) than a target reference level. After the strict erase verify, strings of memory cells that pass the strict erase verify are locked out from a next erase verify at the target reference level. Locked out strings do not conduct a significant current during erase verify, thus reducing peak current and/or power consumption.

Abstract: A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell.

Abstract: When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.