Patents by Inventor Shih-Chung Lee
Shih-Chung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8526233Abstract: In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.Type: GrantFiled: May 23, 2011Date of Patent: September 3, 2013Assignee: SanDisk Technologies Inc.Inventors: Gerrit Jan Hemink, Shih-Chung Lee, Anubhav Khandelwal, Henry Chin, Guirong Liang, Dana Lee
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Patent number: 8472266Abstract: Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn?2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.Type: GrantFiled: March 31, 2011Date of Patent: June 25, 2013Assignee: SanDisk Technologies Inc.Inventors: Anubhav Khandelwal, Jun Wan, Shih-Chung Lee, Dana Lee
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Publication number: 20120300550Abstract: In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.Type: ApplicationFiled: May 23, 2011Publication date: November 29, 2012Inventors: Gerrit Jan Hemink, Shih-Chung Lee, Anubhav Khandelwal, Henry Chin, Guirong Liang, Dana Lee
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Publication number: 20120250414Abstract: Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn?2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Inventors: Anubhav Khandelwal, Jun Wan, Shih-Chung Lee, Dana Lee
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Patent number: 8218366Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger.Type: GrantFiled: April 18, 2010Date of Patent: July 10, 2012Assignee: SanDisk Technologies Inc.Inventors: Yingda Dong, Shih-Chung Lee, Ken Oowada
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Patent number: 8218367Abstract: When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.Type: GrantFiled: June 7, 2011Date of Patent: July 10, 2012Assignee: SanDisk Technologies Inc.Inventors: Gerrit Jan Hemink, Shih-Chung Lee, Toru Miwa, Yupin Fong, Jun Wan, Ken Oowada
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Patent number: 8189378Abstract: A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected to non-volatile storage elements that may be partially programmed.Type: GrantFiled: September 27, 2006Date of Patent: May 29, 2012Assignee: SanDisk Technologies Inc.Inventors: Gerrit Jan Hemink, Shih-Chung Lee
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Patent number: 8184478Abstract: A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected to non-volatile storage elements that may be partially programmed.Type: GrantFiled: September 27, 2006Date of Patent: May 22, 2012Assignee: SanDisk Technologies Inc.Inventors: Gerrit Jan Hemink, Shih-Chung Lee
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Publication number: 20120100332Abstract: A self bonding floor tile includes a main body and a self bonding layer connected with the main body. The self bonding layer includes an absorbate, a first adhesive and a second adhesive. The first adhesive connects the main body with the self bonding layer. At least a portion of the absorbate extends into the first adhesive, and at least a portion of the second adhesive penetrates into the absorbate for connecting the self bonding layer with a body to be decorated. A method for manufacturing the self bonding floor tile includes: providing a main body; spreading a first adhesive over the main body; providing an absorbate with porous or wick structure, and adding the absorbate to the first adhesive; spreading a second adhesive over the absorbate. The present self bonding floor tile can be quickly installed, easily and partly replaced with low installation and replacement cost.Type: ApplicationFiled: November 11, 2010Publication date: April 26, 2012Applicant: Shanghai Jinka Flooring Technology Co., LTD.Inventors: HSIUNG-TIEH YU, Shih-Chung Lee
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Patent number: 8081519Abstract: An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and recorded as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation applies soft programming pulses to the storage elements until a soft programming verify level is satisfied. Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as starting amplitude, step size or pulse duration.Type: GrantFiled: October 6, 2010Date of Patent: December 20, 2011Assignee: SanDisk Technologies Inc.Inventors: Shih-Chung Lee, Gerrit Jan Hemink
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Publication number: 20110255345Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger.Type: ApplicationFiled: April 18, 2010Publication date: October 20, 2011Inventors: Yingda Dong, Shih-Chung Lee, Ken Oowada
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Publication number: 20110235423Abstract: When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.Type: ApplicationFiled: June 7, 2011Publication date: September 29, 2011Inventors: Gerrit Jan Hemink, Shih-Chung Lee, Toru Miwa, Yupin Fong, Jun Wan, Ken Oowada
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Patent number: 7978527Abstract: When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.Type: GrantFiled: June 3, 2008Date of Patent: July 12, 2011Assignee: SanDisk Technologies Inc.Inventors: Gerrit Jan Hemink, Shih-Chung Lee, Toru Miwa, Yupin Fong, Jun Wan, Ken Oowada
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Publication number: 20110042003Abstract: A method of making a floor panel includes the steps of: providing an adhesive on a release member; laminating or marrying the release member to a bottom layer such that the adhesive is between the release member and the bottom layer; removing a portion of the release member to expose an area of the adhesive; and adhering a top layer to the area such that the top layer is offset with respect to the bottom layer in a direction of length and width and a marginal end portion of a top surface of the bottom layer and a marginal end portion of the bottom surface of the top layer is exposed.Type: ApplicationFiled: August 19, 2010Publication date: February 24, 2011Inventors: Richard H. Balmer, Shih Chung Lee, Dung V. Dao, John R. Eshbach, JR., Heath E. Harrington, Michael E. Buckwalter, Kean M. Anspach
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Publication number: 20110042252Abstract: A packaging system and a method of packaging a plurality of floor panels in a box includes floor panels having a top layer and a bottom layer. The top layer has a top surface with a visible decorative pattern and a bottom surface adhered to a top surface of the bottom layer such that the bottom layer is offset from the top layer in a direction of length and width and a marginal end portion of the top surface of the bottom layer and a marginal end portion of the bottom surface of the top layer is exposed. At least one of the marginal end portions has an adhesive. The floor panels are stacked in the box in pairs. Each of the pairs is stacked such that the top surfaces of the top layers of each of the pairs of the floor panels are facing each other.Type: ApplicationFiled: August 19, 2010Publication date: February 24, 2011Inventors: Richard H. Balmer, Shih Chung Lee, Dung V. Dao, Christopher R. Knafelc, Heath E. Harrington, Kean M. Anspach, Michael E. Buckwalter, John R. Eshbach, JR.
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Publication number: 20110019483Abstract: An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and recorded as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation applies soft programming pulses to the storage elements until a soft programming verify level is satisfied. Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as starting amplitude, step size or pulse duration.Type: ApplicationFiled: October 6, 2010Publication date: January 27, 2011Inventors: Shih-Chung Lee, Gerrit Jan Hemink
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Patent number: 7839690Abstract: An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and recorded as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation applies soft programming pulses to the storage elements until a soft programming verify level is satisfied. Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as starting amplitude, step size or pulse duration.Type: GrantFiled: December 11, 2008Date of Patent: November 23, 2010Assignee: SanDisk CorporationInventors: Shih-Chung Lee, Gerrit Jan Hemink
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Publication number: 20100149881Abstract: An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and recorded as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation applies soft programming pulses to the storage elements until a soft programming verify level is satisfied. Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as starting amplitude, step size or pulse duration.Type: ApplicationFiled: December 11, 2008Publication date: June 17, 2010Inventors: Shih-Chung Lee, Gerrit Jan Hemink
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Patent number: 7675780Abstract: In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the required threshold voltage is reduced. For example, programming time period may be increased with an increase in the voltage level of the pump pulse required. This allows the programming time period of the program pulse to be increased to a value that compensates for the increased charge-up time that is required for the higher amplitude program pulses to reach the desired programming voltage.Type: GrantFiled: January 24, 2008Date of Patent: March 9, 2010Assignee: SanDisk CorporationInventors: Shih-Chung Lee, Toru Miwa
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Publication number: 20090296475Abstract: When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Inventors: Gerrit Jan Hemink, Shih-Chung Lee, Toru Miwa, Yupin Fong, Jun Wan, Ken Oowada