Patents by Inventor Shih-Fan Kuan

Shih-Fan Kuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10593637
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shih-Fan Kuan, Yi-Jen Lo
  • Patent number: 10566332
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh D. Tang
  • Patent number: 10373922
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shih-Fan Kuan, Yi-Jen Lo
  • Publication number: 20190229000
    Abstract: A front opening unified pod (FOUP) includes a container, a plurality of wafer slots, at least one inlet pipe, and at least one outlet pipe. The wafer slots, the inlet pipe, and the outlet pipe are disposed in the container. The inlet pipe has a plurality of exhale openings arranged along the inlet pipe. The outlet pipe has a plurality of inhale openings arranged along the outlet pipe.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 25, 2019
    Inventor: Shih-Fan KUAN
  • Publication number: 20190088606
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Inventors: Shih-Fan Kuan, Yi-Jen Lo
  • Publication number: 20190088658
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Application
    Filed: November 15, 2018
    Publication date: March 21, 2019
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh D. Tang
  • Patent number: 10163909
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
  • Publication number: 20180358315
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 13, 2018
    Inventors: Shih-Fan Kuan, Yi-Jen Lo
  • Publication number: 20180190582
    Abstract: An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. The capacitor is embedded in the organic substrate and includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer between the first electrode layer and the second electrode layer. The first electrode layer electrically connects with the first redistribution layer. The hard mask layer is on the organic substrate. The conductive pillar is embedded in the organic substrate and the hard mask layer and electrically connects with the first redistribution layer. The second redistribution layer is on the hard mask layer and electrically connects with the second electrode layer and the conductive pillar.
    Type: Application
    Filed: January 3, 2017
    Publication date: July 5, 2018
    Inventors: Shing-Yih SHIH, Shih-Fan KUAN, Tieh-Chiang WU
  • Publication number: 20180102366
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Application
    Filed: December 13, 2017
    Publication date: April 12, 2018
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
  • Patent number: 9881924
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
  • Publication number: 20170330882
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 16, 2017
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
  • Publication number: 20170033078
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip, a plurality of first connectors and a conductive contact. The two device regions are formed from the substrate, and the substrate has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface and electrically connected to the two device regions, and the external chip is disposed on the first redistribution layer. The first connectors are interposed between the first redistribution layer and the external chip to interconnect the first redistribution layer and the external chip, and the conductive contact is extended from the second surface to the first surface of the substrate to electrically connect the device region.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Shih-Fan KUAN, Yi-Jen LO
  • Patent number: 9543270
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip, a plurality of first connectors and a conductive contact. The two device regions are formed from the substrate, and the substrate has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface and electrically connected to the two device regions, and the external chip is disposed on the first redistribution layer. The first connectors are interposed between the first redistribution layer and the external chip to interconnect the first redistribution layer and the external chip, and the conductive contact is extended from the second surface to the first surface of the substrate to electrically connect the device region.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: January 10, 2017
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Shih-Fan Kuan, Yi-Jen Lo
  • Publication number: 20160358870
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.
    Type: Application
    Filed: June 4, 2015
    Publication date: December 8, 2016
    Inventors: Shih-Fan KUAN, Yi-Jen LO
  • Publication number: 20160351462
    Abstract: A semiconductor package includes a semiconductor die having an active face. At least one pad is disposed on the active face of the semiconductor die. A molding compound seals the semiconductor die except for the active face. The molding compound has a top surface that is flush with the active face of the semiconductor die. A redistribution layer is formed directly on the top surface of the molding compound and on the active face of the semiconductor die. A warpage-control notch is cut into the molding compound. The warpage-control notch is in close proximity to the semiconductor die.
    Type: Application
    Filed: May 25, 2015
    Publication date: December 1, 2016
    Inventors: Shih-Fan Kuan, Neng-Tai Shih
  • Patent number: 9455243
    Abstract: A silicon interposer includes a silicon substrate having a front side and a rear side opposite to the front side; a first integrated circuit chip disposed in the front side of the silicon substrate; a second integrated circuit chip disposed in the front side of the silicon substrate and being in close proximity to the first integrated circuit chip; a dummy kerf region between the first integrated circuit chip and the second integrated circuit chip; and at least a circuit device disposed in the front side of the silicon substrate within the kerf region.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: September 27, 2016
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Shih-Fan Kuan, Neng-Tai Shih
  • Patent number: 8384191
    Abstract: The present invention discloses a stack capacitor structure and method of making the same. The top plate of the stack capacitor structure is connected to each other through a connecting node. The method of forming the stack capacitor structure includes providing an insulating substrate with a doped insulating material layer disposed therein. Then, the insulating substrate is patterned to form a trench, wherein an inner sidewall of the trench has a first region and a second region and the doped insulating material layer within the second region is entirely removed to form a hole. Later, a top plate is formed to surround the inner sidewall of the trench, and the top plate fills in the hole. Next, a capacitor dielectric layer is formed to surround the top plate. Finally, a storage node is formed to fill up the trench.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: February 26, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Shih-Fan Kuan
  • Publication number: 20120299153
    Abstract: The present invention discloses a stack capacitor structure and method of making the same. The top plate of the stack capacitor structure is connected to each other through a connecting node. The method of forming the stack capacitor structure includes providing an insulating substrate with a doped insulating material layer disposed therein. Then, the insulating substrate is patterned to form a trench, wherein an inner sidewall of the trench has a first region and a second region and the doped insulating material layer within the second region is entirely removed to form a hole. Later, a top plate is formed to surround the inner sidewall of the trench, and the top plate fills in the hole. Next, a capacitor dielectric layer is formed to surround the top plate. Finally, a storage node is formed to fill up the trench.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Inventor: Shih-Fan Kuan
  • Patent number: 7749856
    Abstract: A method of fabricating a storage node with a supported structure is provided. A dielectric stacked comprising an etch stop layer, a first dielectric layer, a support layer and a second dielectric layer is formed on a substrate. An opening is etched into the dielectric stacked. A conductive layer is formed on the second dielectric layer and inside the opening. The conductive layer directly above the second dielectric layer is removed to form columnar node structure. The second dielectric layer is then removed. A spacer layer is deposited on the support layer and the columnar node structure. A tilt-angle implant is performed to implant dopants into the spacer layer. The undoped spacer layer is removed to form a hard mask. The support layer not covered by the hard mask is etched away to expose the first dielectric layer. The first dielectric layer and the hard mask are removed.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: July 6, 2010
    Assignee: Nanya Technology Corp.
    Inventors: Shih-Fan Kuan, Le-Tien Jung