Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer and a third nitride layer in sequence over the substrate; forming a first opening and a second opening, wherein the first opening exposes a first landing pad in the substrate, and the second opening exposes a second landing pad in the substrate; forming a first electrode in the first opening and a second electrode in the second opening; removing the first sacrificial layer and the second sacrificial layer concurrently; and forming a conductive layer, conformal to the first electrode, the second electrode, the first nitride layer, the second nitride layer and the third nitride layer.

Abstract: The present disclosure provides a semiconductor structure with a single side capacitor. The semiconductor structure includes a substrate having a first landing pad therein, and a first capacitor disposed over the substrate. The first capacitor includes: a first electrode, disposed over and extending vertically away from the first landing pad; a first dielectric layer, at least partially surrounding the first electrode, wherein the first electrode is shorter than the first dielectric layer; and a second electrode, surrounding the first dielectric layer and the first electrode.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A front opening unified pod (FOUP) includes a container, a plurality of wafer slots, at least one inlet pipe, and at least one outlet pipe. The wafer slots, the inlet pipe, and the outlet pipe are disposed in the container. The inlet pipe has a plurality of exhale openings arranged along the inlet pipe. The outlet pipe has a plurality of inhale openings arranged along the outlet pipe.

Abstract: A method of manufacturing a semiconductor structure includes forming a precursor structure on a substrate. The precursor structure includes a first conductive structure, a first spacer layer, and a spacer oxide layer sequentially on the substrate. The spacer oxide layer exposes a top surface of the first spacer layer. The spacer oxide layer is then recessed. A second spacer layer is formed to cover the spacer oxide layer and the first spacer layer. A portion of the second spacer layer and a portion of the spacer oxide layer are then etched to expose the lateral portion of the first spacer layer. The remaining spacer oxide layer is etched to form an air gap between the first spacer layer and the second spacer layer. A third spacer layer is formed on the lateral portion of the first spacer layer to seal the air gap.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

Abstract: An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. The capacitor is embedded in the organic substrate and includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer between the first electrode layer and the second electrode layer. The first electrode layer electrically connects with the first redistribution layer. The hard mask layer is on the organic substrate. The conductive pillar is embedded in the organic substrate and the hard mask layer and electrically connects with the first redistribution layer. The second redistribution layer is on the hard mask layer and electrically connects with the second electrode layer and the conductive pillar.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A front opening unified pod (FOUP) includes a container, a plurality of wafer slots, at least one inlet pipe, and at least one outlet pipe. The wafer slots, the inlet pipe, and the outlet pipe are disposed in the container. The inlet pipe has a plurality of exhale openings arranged along the inlet pipe. The outlet pipe has a plurality of inhale openings arranged along the outlet pipe.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.