Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, in which the fin-shaped structure comprises a top portion and a bottom portion; and forming a doped layer and a first liner around the bottom portion of the fin-shaped structure.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a material layer on the substrate; forming a plurality of first mandrels on the material layer of the first region and the second region; forming first spacers adjacent to the first mandrels; forming a hard mask on the first region; trimming the first spacers on the second region; removing the first mandrels; using the first spacers to remove part of the material layer for forming a plurality of second mandrels; forming second spacers adjacent to the second mandrels; removing the second mandrels; and using the second spacers to remove part of the substrate for forming a plurality of fin-shaped structures.

Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, in which the fin-shaped structure comprises a top portion and a bottom portion; and forming a doped layer and a first liner around the bottom portion of the fin-shaped structure.

Abstract: A nanowire transistor device includes a substrate, a plurality of nanowires formed on the substrate, and a gate surrounding at least a portion of each nanowire. The nanowires respectively include a first semiconductor core and a second semiconductor core surrounding the first semiconductor core. A lattice constant of the second semiconductor core is different from a lattice constant of the first semiconductor core.

Abstract: The present invention provides a method for forming trenches. First, a mandrel layer is formed on a substrate, wherein the mandrel layer comprises a stop layer and a sacrificial layer. A spacer is formed on at least a sidewall of the mandrel layer, following by forming a material layer on the substrate for covering the spacer and the mandrel layer. After performing a removing process to remove apart of the material layer, apart of the spacer and the sacrificial layer; the spacer is removed to form at least one first trench in the remaining material layer and the mandrel.

Abstract: The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins and second fins are formed in the active region, and a plurality of dummy fins are formed in the dummy region and the active region. A first active region is provided in the active region. A revised first active region is formed by extending the first active region to cover at least one adjacent dummy fin. Next, a first dummy region is provided in the dummy region. A first mask layout is formed by combining the revised first active region and the first dummy region. A first patterned mask layer is formed by using the first mask layout. A first epitaxial process is performed for the first fins and the dummy fins exposed by the first patterned mask layer.

Abstract: The present invention provides a method for forming trenches. First, a mandrel layer is formed on a substrate, wherein the mandrel layer comprises a stop layer and a sacrificial layer. A spacer is formed on at least a sidewall of the mandrel layer, following by forming a material layer on the substrate for covering the spacer and the mandrel layer. After performing a removing process to remove apart of the material layer, apart of the spacer and the sacrificial layer; the spacer is removed to form at least one first trench in the remaining material layer and the mandrel.

Abstract: A semiconductor device is provided. The semiconductor device includes an active fin region, at least a gate strip, and a dummy fin region. The active fin region comprises at least an active fin. The gate strip is formed on the active fin region and extending across the active fin. The dummy fin region, comprising a plurality of dummy fins, is formed on two sides of the active fin region, and the dummy fins are formed on two sides of the gate strip.

Abstract: A semiconductor integrated device includes a substrate having an active region defined thereon, a plurality of active fins positioned in the active region, and a plurality of first protecting fins surrounding the active region. Each of the plurality of active fins extends along a first direction and includes a first length along the first direction. The plurality of first protecting fins extend along the first direction. One of the plurality of first protecting fins immediately adjacent to the active region has a second length along the first direction, and the second length is longer than the first length.

Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.

Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.

Abstract: A fabrication method of a semiconductor device includes the following steps. First, sacrificial patterns are formed on a substrate and a space is formed on the sidewalls of each sacrificial pattern. Then, the sacrificial patterns are removed and patterns of the spacers are transferred into the substrate to form a fin structure. The fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. Subsequently, a gate structure, source/drain structures, and an electrical connecting structure are formed sequentially on the substrate. The gate structure overlaps portions of the horizontal fin structure. The source/drain structures are respectively on each side of the gate structure. The electrical connecting structure directly covers the horizontal fin structure and the vertical fin structure.

Abstract: A semiconductor integrated device includes a substrate having an active region defined thereon, a plurality of active fins positioned in the active region, and a plurality of first protecting fins surrounding the active region. Each of the plurality of active fins extends along a first direction and includes a first length along the first direction. The plurality of first protecting fins extend along the first direction. One of the plurality of first protecting fins immediately adjacent to the active region has a second length along the first direction, and the second length is longer than the first length.

Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.

Abstract: A semiconductor integrated device includes a substrate, a plurality of active fins, and a plurality of first protecting fins. The substrate includes an active region, and the active fins are positioned in the active region. The active region is surrounded by the first protecting fins. The active fins and the first protecting fins all extend along a first direction.

Abstract: A fabrication method of a semiconductor device includes the following steps. First, sacrificial patterns are formed on a substrate and a space is formed on the sidewalls of each sacrificial pattern. Then, the sacrificial patterns are removed and patterns of the spacers are transferred into the substrate to form a fin structure. The fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. Subsequently, a gate structure, source/drain structures, and an electrical connecting structure are formed sequentially on the substrate. The gate structure overlaps portions of the horizontal fin structure. The source/drain structures are respectively on each side of the gate structure. The electrical connecting structure directly covers the horizontal fin structure and the vertical fin structure.

Abstract: A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. The substrate has a first region and a second region. A portion of the horizontal fin structure and the vertical fin structure are disposed in the first region, and the electrical contact structure directly covers the horizontal fin structure and the vertical fin structure within the first region. The gate structure partially overlaps the horizontal fin structure within the second region.

Abstract: A semiconductor device is provided. The semiconductor device includes an active fin region, at least a gate strip, and a dummy fin region. The active fin region comprises at least an active fin. The gate strip is formed on the active fin region and extending across the active fin. The dummy fin region, comprising a plurality of dummy fins, is formed on two sides of the active fin region, and the dummy fins are formed on two sides of the gate strip.