Abstract: The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins and second fins are formed in the active region, and a plurality of dummy fins are formed in the dummy region and the active region. A first active region is provided in the active region. A revised first active region is formed by extending the first active region to cover at least one adjacent dummy fin. Next, a first dummy region is provided in the dummy region. A first mask layout is formed by combining the revised first active region and the first dummy region. A first patterned mask layer is formed by using the first mask layout. A first epitaxial process is performed for the first fins and the dummy fins exposed by the first patterned mask layer.

Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.

Abstract: A semiconductor integrated device includes a substrate, a plurality of active fins, and a plurality of first protecting fins. The substrate includes an active region, and the active fins are positioned in the active region. The active region is surrounded by the first protecting fins. The active fins and the first protecting fins all extend along a first direction.

Abstract: A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. The substrate has a first region and a second region. A portion of the horizontal fin structure and the vertical fin structure are disposed in the first region, and the electrical contact structure directly covers the horizontal fin structure and the vertical fin structure within the first region. The gate structure partially overlaps the horizontal fin structure within the second region.

Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a substrate is provided and a plurality of fin structures, a plurality of first dummy fin structures and a plurality of second dummy fin structures are formed on the substrate; a first patterned photoresist is used as a hard mask to perform a first etching process to remove each first dummy fin structure; then a second patterned photoresist is used as a hard mask to perform a second etching process to remove each second dummy fin structure, wherein the pattern density of the first patterned photoresist is higher than the pattern density of the second patterned.

Abstract: A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.

Abstract: A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.

Abstract: A plane MOS includes a substrate, an insulator layer whose surface is substantially parallel with the surface of the substrate disposed on the substrate, a gate, a source and a drain directly disposed on the insulator layer and a gate channel disposed between the source and the drain and contacting the gate.

Abstract: A method of manufacturing an electrically erasable non-volatile memory is suitable for use on a substrate. The method includes the following steps. First, a tunnel oxide layer is formed on the substrate. A floating gate and a silicon oxide layer/silicon nitride/silicon oxide layer is formed in order on the tunnel oxide layer. Next, a first oxide layer and a silicon nitride spacer are formed in order on the sidewalls of the floating gate. A second oxide layer is formed along the surface of the above entire structure. A third oxide layer is formed on the substrate on both sides of the silicon nitride spacer by oxidation. A patterned conductive layer on the substrate to serve as a control gate and a select transistor gate is formed above the substrate. Using the select transistor gate as a mask, the exposed part of the third oxide layer is removed to make the residual third oxide layer serve as a gate oxide layer of the select transistor.

Abstract: The present invention is a method of fabricating a self-aligned split gate of flash memory. Aligned layers are formed on predetermined source regions and predetermined drain regions in advance. Spacers are formed on the sidewalls of the aligned layers. An etching rate of the spacers is different from an etching rate of the aligned layers. Therefore, if misalignment occurs during the patterning process to form a split control gate layer, the spacers also can be left after the aligned layer is removed. The remaining spacers serves as a implant mask during the implantion for the sources and the drains formation, so that the sources and the drains are formed in the respective positions of the aligned layers by self-alignment.

Abstract: A method for fabricating a gate structure which has gate dielectric layers of different thicknesses. Since the conducting layer and the protective layer are formed respectively on the dielectric layer after the formation the dielectric layer, the dielectric layer and the photoresist involved in the photolithographic etching are effectively isolated from each other. Also, the dielectric layer is formed by performing oxidation once, so the dielectric layer formed as such has different compositions from that of the dielectric layer formed by double oxidation. Thus, the contamination of the dielectric layer by the photoresist is greatly reduced while the quality and reliability of the dielectric layer are greatly improved.