Abstract: A method for manufacturing a semiconductor device includes: forming a dummy gate structure on a semiconductor substrate, the dummy gate structure including a lower portion disposed on the semiconductor substrate and an upper portion disposed on the lower portion and opposite to the semiconductor substrate; and trimming the lower portion of the dummy gate structure by an etching process such that the lower portion of the dummy gate structure has a width less than that of the upper portion of the dummy gate structure.

Abstract: An algorithm method for deep reinforcement learning includes initializing an environment and a model; executing an experience collection process and a network update process in parallel, and determining whether the experience collection process and the network update process have reached a termination condition; and continuing executing the experience collection process and the network update process in parallel in response to neither of the experience collection process and the network update processes has met the termination conditions; and stopping executing the experience collection process and the network update process in response to one of the experience collection processes and the network update process having met the termination conditions.

Abstract: A vehicle display apparatus includes a cover plate, a display module, a frameless backlight module, a housing, a main circuit board, and a mounting bracket. The display module has a cable located in a non-visible area. The frameless backlight module is disposed on a side of the display module away from the cover plate. The housing includes a side wall, a first step, and a second step. The side wall laterally covers the cover plate. The first step supports the cover plate. The first step has a through hole. The second step supports the frameless backlight module. The main circuit board is disposed on a back surface of the housing. The cable is connected to the main circuit board through the through hole. The mounting bracket covers the main circuit board. The side wall laterally covers a connecting portion between the mounting bracket and the housing.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first fin and a gate electrode. The first fin extends along a first direction. The gate electrode has a sidewall extending along a second direction different from the first direction. The sidewall of the gate electrode defines an indentation adjacent to the first fin in a top view.

Abstract: A sidewall protection layer is formed on sidewall spacers of a dummy gate structure of a semiconductor device prior to etching an underlying fin structure to form a source/drain recess. The sidewall protection layer enables the profile of the source/drain recess to be precisely controlled so that etching into residual dummy gate material near the source/drain recess is minimized or prevented. The sidewall protection layer may be removed or retained in the semiconductor device after formation of the source/drain recess. The sidewall protection layer reduces the likelihood of the source/drain regions of the semiconductor device contacting the metal gate structures of the semiconductor device after the dummy gate structures are replaced with the metal gate structures. Thus, the sidewall protection layer reduces the likelihood of electrical shorting between the source/drain regions and the metal gate structures.

Abstract: Methods for forming a dielectric isolation region between two active regions are disclosed herein. A mandrel is formed on a substrate, then etched to form a trench. Spacers are formed on the sidewalls of the mandrel. The mandrel is removed, and the substrate is etched to form fins extending in a first direction in the two active regions, and of fins extending in a second direction. A mask is formed that exposes the substrate between the fins extending in the second direction. The substrate is etched to form a trench. The trench is filled with a dielectric material up to the top of the fins to form the dielectric isolation region. The methods provide better depth control during etching between the two active regions, and also permit the trench to extend deeper into the substrate due to reduced depth/width ratios during the etching steps.

Abstract: An electronic device includes a circuit board, a shielding member, and a testing pin. The circuit board includes a grounding area. The shielding member is located on a side of the circuit board and includes a shielding layer and an insulating layer. The shielding layer is electrically connected to the grounding area. The insulating layer is located on a side of the shielding layer away from the circuit board. The testing pin is disposed on the circuit board and electrically connected to the shielding layer.

Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.

Abstract: A chip-assisted design device and a method for constructing a chip characteristic distribution model. The apparatus includes a database and a processor. The database has a first chip characteristic distribution image data generated based on a wafer fabrication process data of a current process, wherein the first chip characteristic distribution image data represents a gradient distribution of at least one chip characteristic in one of the wafers produced through current fabrication process. The processor is coupled to the database. A second chip characteristic image data generated based on the first chip characteristic image data is used as a reference data for predicting the future wafer fabrication process, and the reference data is provided to the current fabrication process to evaluate or correct the first chip characteristic image.

Abstract: A display device includes a protection assembly and an outer frame. The protection assembly includes a cover plate and an elastic structure. The elastic structure includes a first adhesive layer, a second adhesive layer, and an elastic layer. The first adhesive layer is adhered to the cover plate. The elastic layer is disposed between the first adhesive layer and the second adhesive layer. The outer frame is adhered to the second adhesive layer. A modulus of elasticity of the elastic structure is between 120 N/compression % and 200 N/compression %. A peel adhesive force between the second adhesive layer and the outer frame is between 8 N/25 mm and 100 N/25 mm.

Abstract: A device and a method for integrated circuit assistance design, and a method for constructing an electrical performance gradient model are provided. The device includes a database and a processor. The database has an electrical performance gradient model. The electrical performance gradient model represents a gradient distribution of an electrical performance in a wafer. The processor is coupled to the database. The processor analyzes a designed circuit by using the electrical performance gradient model.

Abstract: An electronic device includes a circuit board, a shielding member, and a testing pin. The circuit board includes a grounding area. The shielding member is located on a side of the circuit board and includes a shielding layer and an insulating layer. The shielding layer is electrically connected to the grounding area. The insulating layer is located on a side of the shielding layer away from the circuit board. The testing pin is disposed on the circuit board and electrically connected to the shielding layer.

Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.

Abstract: A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer.

Abstract: A display apparatus includes display unit and an optical compensation film. The display unit includes an upper polarizer. The optical compensation film is located at a side of the upper polarizer facing an external environment. The optical compensation film includes a linear polarizer. An absolute value of an axial angle difference between the linear polarizer and the upper polarizer is in a range from 0 degrees to 10 degrees.

Abstract: An edge ring, for a plasma etcher, may include a circular bottom portion with an opening sized to receive an electrostatic chuck supporting a semiconductor device, and a circular top portion integrally connected to a first top part of the circular bottom portion. The edge ring may include a circular chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion. The circular chamfer portion may include an inner surface that is angled radially outward from the opening at less than ninety degrees.

Abstract: A device and a method for integrated circuit assistance design, and a method for constructing an electrical performance gradient model are provided. The device includes a database and a processor. The database has an electrical performance gradient model. The electrical performance gradient model represents a gradient distribution of an electrical performance in a wafer. The processor is coupled to the database. The processor analyzes a designed circuit by using the electrical performance gradient model.

Abstract: A setup time and hold time detection system including a monitoring unit and a processing unit. The monitoring unit is configured to detect multiple setup times and multiple hold times of multiple test circuits through a source clock signal. The processing unit is configured to record multiple setup times and multiple hold times as multiple detection data. The processing unit is further configured to select a first part of the detection data as multiple first detection data to establish an estimation model. The processing unit is further configured to select a second part of the detection data as multiple second detection data, and compare the second detection data and multiple estimation results generated by the estimation model to obtain an error value of the estimation model.

Abstract: A setup time and hold time detection system including a monitoring unit and a processing unit. The monitoring unit is configured to detect multiple setup times and multiple hold times of multiple test circuits through a source clock signal. The processing unit is configured to record multiple setup times and multiple hold times as multiple detection data. The processing unit is further configured to select a first part of the detection data as multiple first detection data to establish an estimation model. The processing unit is further configured to select a second part of the detection data as multiple second detection data, and compare the second detection data and multiple estimation results generated by the estimation model to obtain an error value of the estimation model.

Abstract: An edge ring, for a plasma etcher, may include a circular bottom portion with an opening sized to receive an electrostatic chuck supporting a semiconductor device, and a circular top portion integrally connected to a first top part of the circular bottom portion. The edge ring may include a circular chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion. The circular chamfer portion may include an inner surface that is angled radially outward from the opening at less than ninety degrees.