Abstract: A light emitting diode device includes a substrate, a conductive via, first and second conductive pads, a driving chip, a flat layer, a redistribution layer, a light emitting diode, and an encapsulating layer. The substrate has a first surface and a second surface opposite thereto. The conductive via penetrates from the first surface to the second surface. The first and second conductive pads are respectively disposed on the first and second surface and in contact with the conductive via. The driving chip is disposed on the first surface. The flat layer is disposed over the first surface and covers the driving chip and the first conductive pad. The redistribution layer is disposed on the flat layer and electrically connects to the driving chip. The light emitting diode is flip-chip bonded to the redistribution layer. The encapsulating layer covers the redistribution layer and the light emitting diode.

Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, micro light emitting elements, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting elements are disposed on the first adhesive layer and have a first surface facing to the first adhesive layer and an opposing second surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting elements and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A thickness of the flexible substrate is less than 100 um.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes channel structures vertically stacked over a substrate and a source/drain structure laterally attached to the channel structures in the first direction. The semiconductor structure also includes a dielectric wall structure laterally attached to the channel structures in the second direction. The second direction is different from the first direction. In addition, the dielectric wall structure includes a bottom portion and a cap layer formed over the bottom portion. The semiconductor structure also includes an isolation feature vertically overlapping the cap layer of the dielectric wall structure and a gate structure formed around the channel structures and covering a sidewall of the isolation feature.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

Abstract: A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a first substrate, a first interlayer dielectric (ILD) layer on the first MOS transistor, a second substrate on the first ILD layer, and a second MOS transistor on a second substrate. Preferably, the semiconductor device includes a static random access memory (SRAM) and the SRAM includes a first pull-up device, a second pull-up device, a first pull-down device, a second pull-down device, a first pass-gate device, a second pass-gate device, a read port pull-down device, and a read port pass-gate device, in which the read port pull-down device includes the first MOS transistor and the read port pass-gate device includes the second MOS transistor.

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

Abstract: A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

Abstract: A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a first substrate, a first interlayer dielectric (ILD) layer on the first MOS transistor, a second substrate on the first ILD layer, and a second MOS transistor on a second substrate. Preferably, the semiconductor device includes a static random access memory (SRAM) and the SRAM includes a first pull-up device, a second pull-up device, a first pull-down device, a second pull-down device, a first pass-gate device, a second pass-gate device, a read port pull-down device, and a read port pass-gate device, in which the read port pull-down device includes the first MOS transistor and the read port pass-gate device includes the second MOS transistor.

Abstract: A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

Abstract: A method and a system for determining a discharging process of a battery are provided. The method includes the following steps. Measuring charging/discharging information of the battery. Calculating a charging/discharging characteristic of the battery according to the charging/discharging information. Aligning the charging/discharging characteristic of the battery according to a comparison characteristic point of a comparison characteristic to obtain an aligned charging/discharging characteristic. Determining whether the battery is normal according to the aligned charging/discharging characteristic or a coulombic efficiency of the battery. Calculating a safety probability of the battery according to the aligned charging/discharging characteristic and resistance of an internal short circuit of the battery when the battery is determined as abnormal. Determining a discharging process of the battery according to the safety probability of the battery.

Abstract: A fire control device comprises a box, a power wire, a pressure relieving check valve, a fire extinguishing check valve and a fire extinguisher. The box is configured to accommodate a battery system, and the power wire is configured to couple to the battery system. The pressure relieving check valve and the fire extinguishing check valve extend through the box, and a state of the pressure relieving check valve is switched between open and closed states according to a pressure difference between an inside and an outside of the box. A state of the fire extinguishing check valve is switched between open and close states according to a pressure difference between the inside and the outside of the box. The fire extinguisher is connected to the pressure relieving check valve. The fire extinguisher is switched between starting and stopping modes according to the state of the pressure relieving check valve.

Abstract: A method and a system for detecting resistance of an internal short circuit of a battery are provided. The method includes the following steps. Measuring charging/discharging information of the battery. Calculating a charging/discharging characteristic of the battery according to the charging/discharging information. Aligning the charging/discharging characteristic of the battery according to a comparison characteristic point of a comparison characteristic to obtain an aligned charging/discharging characteristic. Determining whether the battery is normal according to the aligned charging/discharging characteristic or a coulombic efficiency of the battery; and when the battery is determined as abnormal, calculating aligned charging/discharging information according to the aligned charging/discharging characteristic, and calculating the resistance of the internal short circuit of the battery according to the aligned charging/discharging information.

Abstract: A fire control device comprises a box, a power wire, a pressure relieving check valve, a fire extinguishing check valve and a fire extinguisher. The box is configured to accommodate a battery system, and the power wire is configured to couple to the battery system. The pressure relieving check valve and the fire extinguishing check valve extend through the box, and a state of the pressure relieving check valve is switched between open and closed states according to a pressure difference between an inside and an outside of the box. A state of the fire extinguishing check valve is switched between open and close states according to a pressure difference between the inside and the outside of the box. The fire extinguisher is connected to the pressure relieving check valve. The fire extinguisher is switched between starting and stopping modes according to the state of the pressure relieving check valve.

Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.

Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.

Abstract: A method and a system for detecting resistance of an internal short circuit of a battery are provided. The method includes the following steps. Measuring charging/discharging information of the battery. Calculating a charging/discharging characteristic of the battery according to the charging/discharging information. Aligning the charging/discharging characteristic of the battery according to a comparison characteristic point of a comparison characteristic to obtain an aligned charging/discharging characteristic. Determining whether the battery is normal according to the aligned charging/discharging characteristic or a coulombic efficiency of the battery; and when the battery is determined as abnormal, calculating aligned charging/discharging information according to the aligned charging/discharging characteristic, and calculating the resistance of the internal short circuit of the battery according to the aligned charging/discharging information.

Abstract: A method and a system for determining a discharging process of a battery are provided. The method includes the following steps. Measuring charging/discharging information of the battery. Calculating a charging/discharging characteristic of the battery according to the charging/discharging information. Aligning the charging/discharging characteristic of the battery according to a comparison characteristic point of a comparison characteristic to obtain an aligned charging/discharging characteristic. Determining whether the battery is normal according to the aligned charging/discharging characteristic or a coulombic efficiency of the battery. Calculating a safety probability of the battery according to the aligned charging/discharging characteristic and resistance of an internal short circuit of the battery when the battery is determined as abnormal. Determining a discharging process of the battery according to the safety probability of the battery.

Abstract: A battery module includes a crystal lattice type battery, a detection circuit, a control circuit and an excitation circuit. The detection circuit is electrically coupled to the battery. The control circuit is electrically coupled to the detection circuit. The excitation circuit is electrically coupled to the control circuit and the battery. When the battery is charged or discharged, the detection circuit is configured to detect an impedance of the battery. The control circuit is configured to compare the impedance and a threshold. And the control circuit is configured to produce a control signal. The excitation circuit is configured to selectively provide an excitation signal to the battery according to the control signal.