Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.

Abstract: A semiconductor structure includes a substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are over the substrate. The semiconductor layers are between the source/drain features. The metal oxide layers are on top surfaces and bottom surfaces of the semiconductor layers. The gate structure covers and is in contact with center portions of the metal oxide layers on top surfaces and bottom surfaces of the semiconductor layers.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive pad over the substrate. The chip structure includes a passivation layer covering the substrate and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The first etch stop layer and the first buffer layer are made of different materials. The chip structure includes a second etch stop layer over the first buffer layer. The second etch stop layer and the first buffer layer are made of different materials.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. A second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. A first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. A second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. A plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.

Abstract: An exemplary embodiment of the invention provides an image processing method for a virtual reality display system. The method includes: enabling a first shared buffer and a second shared buffer; performing an image capturing operation to obtain a first image from a virtual reality scene; storing the first image to the first shared buffer; in response to that the storing of the first image is finished, reading the first image from the first shared buffer; performing a depth estimation operation on the first image to obtain depth information corresponding to the first image; storing the depth information to the second shared buffer; in response to that the storing of the depth information is finished, reading the depth information from the second shared buffer; performing an image generation operation according to the depth information to generate a pair of second images corresponding to the virtual reality scene; and outputting the pair of second images by a display of the virtual reality display system.

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

Abstract: A Static Radom Access Memory (SRAM) cell includes a pass-gate transistor and a pull-down transistor. The pass-gate transistor includes a first active region and a first gate structure engaging the first active region. The pull-down transistor includes a second active region and a second gate structure engaging the second active region. The SRAM cell further includes a first isolation feature abutting the first gate structure and a second isolation feature abutting the second gate structure. The first isolation feature is spaced from the first active region of the pass-gate transistor for a first distance. The second isolation feature is spaced from the second active region of the pull-down transistor for a second distance that is larger than the first distance.

Abstract: An image presenting method and a display device are disclosed. The method includes: defining one vision region in a display interface of a foldable display via a first application programming interface; detecting a physical status of the foldable display; dividing the vision region into a first sub-vision region and a second sub-vision region in response to that the physical status of the foldable display is a folded status; and presenting a first desktop image and a second desktop image in the first sub-vision region and the second sub-vision region respectively via a second application programming interface, wherein one of the first desktop image and the second desktop image includes a toolbar image, and a presenting position of the toolbar image in the first sub-vision region or the second sub-vision region is variable.

Abstract: An image presenting method and a display apparatus are provided. The method includes: presenting at least one virtual screen and a tool bar image in a display interface of a rollable display; detecting a physical status of the rollable display; and adjusting presenting positions of the tool bar image and the at least one virtual screen in the display interface in response to a change in the physical status.

Abstract: An imaging method, an electronic device and a video conference system are provided. The imaging method is used for performing video conference on a display. The imaging method includes the following steps. At least one video conference stream is received. When a 3D modeling command is received, a plurality of 2D frames shown on the display are captured. Based on the 2D frames, at least one 3D model is built. When a rending command corresponding to a viewing angle information is received, an adjusted image corresponding to the viewing angle information is rendered according to at least one 3D model.

Abstract: Semiconductor devices having improved source/drain features and methods for fabricating such are disclosed herein. An exemplary device includes a semiconductor layer stack disposed over a mesa structure of a substrate. The device further includes a metal gate disposed over the semiconductor layer stack and an inner spacer disposed on the mesa structure of the substrate. The device further includes a first epitaxial source/drain feature and a second epitaxial source/drain feature where the semiconductor layer stack is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The device further includes a void disposed between the inner spacer and the first epitaxial source/drain feature.

Abstract: A fabricating method of a non-enzyme sensor element includes a printing step, a coating step and an electroplating step. In the printing step, a conductive material is printed on a surface of a substrate to form a working electrode, a reference electrode and an auxiliary electrode, and a porous carbon material is printed on the working electrode to form a porous carbon layer. In the coating step, a graphene film material is coated on the porous carbon layer of the working electrode to form a graphene layer. In the electroplating step, a metal is electroplated on the graphene layer by a pulse constant current to form a catalyst layer including a metal oxide.

Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.

Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.

Abstract: A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (Vt) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.

Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. A second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. A first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. A second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. A plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The first etch stop layer and the first buffer layer are made of different materials. The chip structure includes a second etch stop layer over the first buffer layer. The second etch stop layer and the first buffer layer are made of different materials. The chip structure includes a device element over the second etch stop layer.