Abstract: A semiconductor device comprises a memory macro including a well pick-up (WPU) area oriented lengthwise along a first direction, and memory bit areas adjacent to the WPU area. In the WPU area, the memory macro includes n-type and p-type wells arranged alternately along the first direction with well boundaries between adjacent wells; gate structures over the wells and oriented lengthwise along the first direction; a first dielectric layer disposed at each of the well boundaries; first contact features disposed over one of the p-type wells; and second contact features disposed over one of the n-type wells. From a top view, the first dielectric layer extends along a second direction perpendicular to the first direction and separates all the gate structures in the first WPU area, the first contact features are disposed between the gate structures, and the second contact features are disposed between the gate structures.

Abstract: A web page access method includes the following steps. A universal window platform interface receives a first command. The first command is transmitted to a server through a processor. Hardware is accessed or enabled by the server, according to the first command. A second command is received through an icon. The second command is transmitted to the server through the processor. The server accesses or enables the hardware according to the second command. The universal window platform interface and the game bar interface are constructed using a progressive web application.

Abstract: A method for generating stereoscopic images is provided. The method includes: creating a three-dimensional mesh to obtain a stereoscopic scene and capturing a two-dimensional image of the stereoscopic scene; performing image preprocessing to obtain a first image in response to the two-dimensional image not being a side-by-side image; utilizing a graphics processing pipeline to perform depth estimation on the first image to obtain a depth image, to update the three-dimensional mesh according to a depth setting of the depth image, and to map the three-dimensional mesh to a corresponding coordinate system; utilizing the graphics processing pipeline to project the first image onto the mapped three-dimensional mesh to obtain an output three-dimensional mesh, and to capture an output side-by-side image from the output three-dimensional mesh; and utilizing the graphics processing pipeline to weave a left-eye and right-eye image into an output image, and to display the output image.

Abstract: A stereoscopic image generating method is provided. The method includes: processing a first image to obtain depth data of each pixel in the first image, and generating a first depth-information map, wherein the first depth-information map includes depth information corresponding to each pixel; performing uniform processing on a plurality of edge pixels which are within a predetermined width from a plurality of edges of the first depth-information map, so that the processed edge pixels have the same depth information to establish a second depth-information map; setting a pixel offset corresponding to each pixel in the first image based on the depth information corresponding to each pixel of the second depth-information map; performing pixel offset processing on the first image to generate a second image; and outputting the first image and the second image to the display unit to display a stereoscopic image.

Abstract: A method includes forming a first fin protruding from a substrate in a first region of the substrate and a second fin protruding from the substrate in a second region of the substrate, recessing a portion of the first fin, thereby forming a first recess, recessing a portion of the second fin, thereby forming a second recess, depositing a blocking layer in the second recess, growing a base epitaxial layer in the first recess, removing the blocking layer from the second recess, and growing a doped epitaxial layer in the first recess and the second recess. The base epitaxial layer is dopant free. The doped epitaxial layer abuts the first fin in the first region and the second fin in the second region.

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate; forming a first gate structure over the substrate and crossing the first semiconductor fin; forming a second gate structure over the substrate and crossing the second semiconductor fin; forming a first gate spacer on a sidewall of the first gate structure; and forming a second gate spacer on a sidewall of the second gate structure, wherein in a top view, an outer sidewall of the first gate spacer farthest from the first gate structure is coterminous with an outer sidewall of the second gate spacer farthest from the second gate structure, and an inner sidewall of the first gate spacer in contact with the first gate structure is misaligned with an inner sidewall of the second gate spacer in contact with the second gate structure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first set of nanostructures stacked over a substrate and spaced apart from one another, a second set of nanostructures stacked over the substrate and spaced apart from one another, a first source/drain feature adjoining the first set of nanostructures, a second source/drain feature adjoining the second set of nanostructures, a first contact plug landing on and partially embedded in the first source/drain feature, and a second contact plug landing on and partially embedded in the second source/drain feature. A bottom of the first contact plug is lower than a bottom of the second contact plug.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The chip structure includes a second etch stop layer over the first buffer layer. The chip structure includes a device element over the second etch stop layer.

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

Abstract: A semiconductor device structure includes nanostructures disposed over a substrate. The structure also includes a gate structure surrounding the nanostructures. The structure also includes inner spacers disposed over opposite sides of the gate structure. The structure also includes source/drain epitaxial structure disposed over opposite sides of the nanostructures. An air gap is disposed between the inner spacers and the source/drain epitaxial structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

Abstract: A 3D display system and a 3D display method are provided. The 3D display system includes a 3D display, a memory and one or more processors. The memory records a plurality of modules, and the processor accesses and executes the modules recorded by the memory. The modules include a bridge interface module and a 3D display service module. When an application is executed by the processor, the bridge interface module creates a virtual extend screen, and moves the application to the virtual extend screen. The bridge interface module obtains a 2D content frame of the application from the virtual extend screen by a screenshot function. The 3D display service module converts the 2D content frame into a 3D format frame by communicating with a third-party software development kit, and provides the 3D format frame to the 3D display for displaying.

Abstract: A method includes providing a substrate, a source/drain (S/D) feature and semiconductor channel layers over the substrate, a high-k metal gate (HKMG) wrapping around the channel layers, a dielectric cap over the HKMG, a contact etch stop layer (CESL) over the S/D feature and on sidewalls of the dielectric cap and the HKMG, and an interlayer dielectric (ILD) layer over the CESL. The channel layers are spaced one from another along a direction perpendicular to a top surface of the substrate and connect to the S/D feature. The method further includes etching the ILD layer and the CESL to expose a top portion of the S/D feature; etching the S/D feature, resulting in a S/D contact trench, wherein a bottom surface of the S/D contact trench is below an upper surface of a bottommost layer of the channel layers; and forming a metallic contact in the S/D contact trench.

Abstract: A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.

Abstract: A Static Radom Access Memory (SRAM) cell includes a pass-gate transistor and a pull-down transistor. The pass-gate transistor includes a first active region and a first gate structure engaging the first active region. The pull-down transistor includes a second active region and a second gate structure engaging the second active region. The SRAM cell further includes a first isolation feature abutting the first gate structure and a second isolation feature abutting the second gate structure. The first isolation feature is spaced from the first active region of the pass-gate transistor for a first distance. The second isolation feature is spaced from the second active region of the pull-down transistor for a second distance that is larger than the first distance.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.