Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a gate dielectric structure on a substrate. A sidewall spacer is formed around the gate dielectric structure. A metal structure is formed over the gate dielectric structure. A gate body layer is formed over the metal structure. A lower portion of the gate body layer is cupped by the metal structure. A top surface of the gate body layer is vertically offset from a top surface of the metal structure. A conductive via is formed over the metal structure. The conductive via is disposed between outer sidewalls of the gate body layer.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate structure. The semiconductor device further includes a pair of spacer segments on a semiconductor substrate. A high-? gate dielectric structure overlies the semiconductor substrate. The high-? gate dielectric structure is laterally between and borders the spacer segments. The gate structure overlies the high-k gate dielectric structure and has a top surface about even with a top surface of the spacer segments. The gate structure includes a metal structure and a gate body layer. The gate body layer has a top surface that is vertically offset from a top surface of the metal structure and further has a lower portion cupped by the metal structure.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate structure. The semiconductor device further includes a pair of spacer segments on a semiconductor substrate. A high-? gate dielectric structure overlies the semiconductor substrate. The high-? gate dielectric structure is laterally between and borders the spacer segments. The gate structure overlies the high-k gate dielectric structure and has a top surface about even with a top surface of the spacer segments. The gate structure includes a metal structure and a gate body layer. The gate body layer has a top surface that is vertically offset from a top surface of the metal structure and further has a lower portion cupped by the metal structure.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.

Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.