Patents by Inventor Shih-Hao Lo

Shih-Hao Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9252224
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Publication number: 20150270397
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 24, 2015
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Hsieh-Ying Hao
  • Patent number: 9054130
    Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: June 9, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Peng, Chao-Cheng Chen, Ming-Hua Yu, Ying Hao Hsieh, Tze-Liang Lee, Chii-Horng Li, Syun-Ming Jang, Shih-Hao Lo
  • Publication number: 20140367802
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Application
    Filed: August 28, 2014
    Publication date: December 18, 2014
    Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, JUNG-HUI KAO, Yuan-Tien Tu, HUAN-JUST LIN, Chih-Tang Peng, Pei-Ren Jeng, BAO-RU YOUNG, HARRY-HAK-LA Y CHUANG
  • Patent number: 8822283
    Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Hak-Lay Chuang
  • Publication number: 20130056837
    Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Application
    Filed: September 24, 2011
    Publication date: March 7, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Hak-Lay Chuang
  • Publication number: 20110049567
    Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas.
    Type: Application
    Filed: July 22, 2010
    Publication date: March 3, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Eric Peng, Chao-Cheng Chen, Ming-Hua Yu, Ying Hao Hsieh, Tze-Liang Lee, Chii-Horng Li, Syun-Ming Jang, Shih-Hao Lo
  • Publication number: 20060196417
    Abstract: Gas distribution systems for deposition processes and methods of using the same. A substrate support member holding a substrate is disposed in a processing chamber. A plurality of first and second gas nozzles is connected to a gas distribution ring disposed in the processing chamber. The first gas nozzles provide a first reactant gas and include at least first and second outlet apertures. The second gas nozzles provide a second reactant gas and include third outlet apertures. The first outlet aperture is larger than the second outlet aperture, such that the first gas nozzle with the first outlet aperture creates an increased gas flow adjacent to a determined portion of the substrate to increase deposition from the first reactant gas on the determined portion of the substrate.
    Type: Application
    Filed: March 3, 2005
    Publication date: September 7, 2006
    Inventors: Chia-Hui Lin, Shih-Hao Lo, Tsang-Yu Liu, Szu-An Wu, Cheng-Hui Yang, Yi-Fang Lai, Chien Lin