Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A semiconductor structure includes a first well region disposed within a substrate and comprising a first doping type. A conductive structure overlies the first well region. A pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. The pair of first doped regions comprise a second doping type opposite the first doping type. A pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. The pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.

Abstract: A semiconductor device includes a non-volatile memory structure. A layout of metallization layers in the semiconductor device coupled with the non-volatile memory structure is configured to achieve a low likelihood of electromigration in the non-volatile memory structure, particularly at operating temperature parameters associated with demanding applications such as automotive and/or industrial, among other examples. The non-volatile memory structure is electrically coupled with a first metallization layer. The first metallization layer electrically couples the non-volatile memory structure with a second metallization layer that is configured as a write bit line metallization layer for the non-volatile memory structure. The first metallization layer electrically couples the non-volatile memory structure with a third metallization layer above the second metallization layer. The third metallization layer is configured as a read bit line metallization layer for the non-volatile memory structure.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a transistor, and a capacitor. The transistor includes a gate electrode disposed on the substrate. The capacitor is electrically connected to the transistor and includes a capacitor dielectric and a capacitor electrode. The capacitor dielectric and the capacitor electrode are stacked over the gate electrode of the transistor.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.

Abstract: A field effect transistor includes a source region and a drain region embedded in a portion of a semiconductor substrate; a gate dielectric overlying a channel region located between the source region and the drain region; a gate electrode overlying the gate dielectric; a dielectric gate liner laterally surrounding the gate electrode; a inner gate spacer laterally surrounding the dielectric gate liner; a contoured gate capping dielectric including a vertically-extending portion that laterally surrounds the inner gate spacer and a horizontally-extending portion that overlies the gate electrode; and a outer gate spacer laterally surrounding the contoured gate capping dielectric.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A memory device includes a first well region, a second well region, and third well regions. The second well region is interposed between the first region and the third well regions, and the third well regions are separated from one another. The memory device includes floating gates disposed over the first to third well regions, wherein each of the floating gates continuously extends from the first well region to a corresponding one of the third well regions. The memory device includes a bit line write region disposed within the second well region. The bit line write region comprises first source/drain regions on opposite sides of each floating gate. The memory device includes a bit line read region disposed within the second well region and spaced from the bit line write region. The bit line read region comprises second source/drain regions on the opposite sides of each floating gate.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first well region disposed within a substrate and comprising a first doping type. A conductive structure overlies the first well region. A pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. The pair of first doped regions comprise a second doping type opposite the first doping type. A pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. The pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.

Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region.