Patents by Inventor Shih-Hsien Chen
Shih-Hsien Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974367Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.Type: GrantFiled: October 4, 2022Date of Patent: April 30, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chih-Hsien Wang, Ming-Chieh Cheng, Po-Yen Chen, Shih-Chieh Chang, Kuan-Hsien Tu, Xiu-Yi Lin, Ling-Chun Wang
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Patent number: 11955495Abstract: The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.Type: GrantFiled: November 21, 2022Date of Patent: April 9, 2024Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Wen-Hsien Chen
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Publication number: 20240107755Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first well region disposed within a substrate and comprising a first doping type. A conductive structure overlies the first well region. A pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. The pair of first doped regions comprise a second doping type opposite the first doping type. A pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. The pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.Type: ApplicationFiled: December 11, 2023Publication date: March 28, 2024Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Patent number: 11934107Abstract: Embodiments described herein relate to methods of forming layers using maskless based lithography. In these embodiments, the methods implement ladders of dose change such that a geometric shape can be divided into overlaying sections. The overlaying sections can include a different dose of each section such that taper control can be achieved. The taper can be achieved by manipulating the geometry “mask data” into overlaying sections that are exposed by various doses controlled by pixel blending (PB) exposure techniques. To perform the methods described herein, a maskless lithography tool is used. The maskless lithography tool includes a controller that performs software based “mask data” manipulation.Type: GrantFiled: October 9, 2019Date of Patent: March 19, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Shih-Hsien Lee, Tingwei Chiu, Frederick Lie, Jang Fung Chen
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Publication number: 20240077805Abstract: Embodiments described herein relate to methods of forming layers using maskless based lithography. In these embodiments, the methods implement ladders of dose change such that a geometric shape can be divided into overlaying sections. The overlaying sections can include a different dose of each section such that taper control can be achieved. The taper can be achieved by manipulating the geometry “mask data” into overlaying sections that are exposed by various doses controlled by pixel blending (PB) exposure techniques. To perform the methods described herein, a maskless lithography tool is used. The maskless lithography tool includes a controller that performs software based “mask data” manipulation.Type: ApplicationFiled: October 9, 2019Publication date: March 7, 2024Inventors: Shih-Hsien LEE, Tingwei CHIU, Frederick LIE, Jang Fung CHEN
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Patent number: 11854621Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.Type: GrantFiled: August 27, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chen-Ming Huang, Wen-Tuo Huang, ShihKuang Yang, Yu-Chun Chang, Shih-Hsien Chen, Yu-Hsiang Yang, Yu-Ling Hsu, Chia-Sheng Lin, Po-Wei Liu, Hung-Ling Shih, Wei-Lin Chang
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Patent number: 11844213Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.Type: GrantFiled: June 30, 2022Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20230335196Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.Type: ApplicationFiled: June 20, 2023Publication date: October 19, 2023Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
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Publication number: 20230230835Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.Type: ApplicationFiled: September 1, 2022Publication date: July 20, 2023Inventors: Po-Chun SHAO, Shih-Hsien CHEN, Ping-Lung YU
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Patent number: 11664333Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.Type: GrantFiled: November 24, 2020Date of Patent: May 30, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang
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Publication number: 20230062874Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Chen-Ming HUANG, Wen-Tuo HUANG, ShihKuang YANG, Yu-Chun CHANG, Shih-Hsien CHEN, Yu-Hsiang YANG, Yu-Ling HSU, Chia-Sheng LIN, Po-Wei LIU, Hung-Ling SHIH, Wei-Lin CHANG
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Publication number: 20220415914Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.Type: ApplicationFiled: August 23, 2021Publication date: December 29, 2022Inventors: Wen-Shun Lo, Tai-Yi Wu, Shih-Hsien Chen, Ying Kit Felix Tsui
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Publication number: 20220336482Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Patent number: 11387242Abstract: An integrated chip includes a first well region, second well region, and third well region disposed within a substrate. The second well region is laterally between the first and third well regions. An isolation structure is disposed within the substrate and laterally surrounds the first, second, and third well regions. A floating gate overlies the substrate and laterally extends from the first well region to the third well region. A dielectric structure is disposed under the floating gate. A bit line write region is disposed within the second well region and includes source/drain regions disposed on opposite sides of the floating gate. A bit line read region is disposed within the second well region, is laterally offset from the bit line write region by a non-zero distance, and includes source/drain regions disposed on the opposite sides of the floating gate.Type: GrantFiled: October 13, 2020Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Patent number: 11152383Abstract: A memory cell may include first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.Type: GrantFiled: March 3, 2020Date of Patent: October 19, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20210280592Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region, second well region, and third well region disposed within a substrate. The second well region is laterally between the first and third well regions. An isolation structure is disposed within the substrate and laterally surrounds the first, second, and third well regions. A floating gate overlies the substrate and laterally extends from the first well region to the third well region. A dielectric structure is disposed under the floating gate. A bit line write region is disposed within the second well region and comprises source/drain regions disposed on opposite sides of the floating gate. A bit line read region is disposed within the second well region, is laterally offset from the bit line write region by a non-zero distance, and comprises source/drain regions disposed on the opposite sides of the floating gate.Type: ApplicationFiled: October 13, 2020Publication date: September 9, 2021Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20210280591Abstract: Various embodiments of the present disclosure are directed towards a memory cell including first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.Type: ApplicationFiled: March 3, 2020Publication date: September 9, 2021Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20210137669Abstract: A polymer fiber tubular structure includes a first pipe element, a second pipe element, and a coil winding structure, wherein the first pipe element includes an inner surface and an outer surface and is composed of silicon-containing polycarbonate type polyurethane elastomer, the second pipe element includes an inner surface and an outer surface and is composed of polycarbonate type polyurethane elastomer. The second pipe element is wrapped on the outer surface of the first pipe element such that the first pipe element and the second pipe element are concentric structures. The coil winding structure is provided for embedding into the outer surface of the first pipe element or into the outer surface of the second pipe element, thereby, the kinking of the polymer fiber tubular structure is to be reduced during use, and the thrombosis can be further avoided when the polymer fiber tubular is used for the human being.Type: ApplicationFiled: April 10, 2020Publication date: May 13, 2021Inventors: Shih-Hsien Chen, Cin-He Chang, Yung-Tai Lin
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Publication number: 20210082839Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.Type: ApplicationFiled: November 24, 2020Publication date: March 18, 2021Applicant: United Microelectronics Corp.Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang
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Patent number: 10892235Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.Type: GrantFiled: September 19, 2018Date of Patent: January 12, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang