Patents by Inventor Shih-Hsien Chen

Shih-Hsien Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220208326
    Abstract: A method for calculating a high risk route of administration is provided. Multiple arrangement routes composed of every two medicines among multiple medicines included in a medical record database are listed. A risk value of each arrangement route is calculated by querying the medical record database based on a specified medication result. A risk score of each arrangement route is calculated according to the risk value, and the arrangement routes are sorted based on the risk scores. Starting from the arrangement route with the highest risk score, N arrangement routes are retrieved and a combination on N of the arrangement routes is performed to obtain multiple strung routes. The number of medicines included in each strung route matches a specified medication number.
    Type: Application
    Filed: July 7, 2021
    Publication date: June 30, 2022
    Applicants: Acer Incorporated, National Yang Ming Chiao Tung University
    Inventors: Pei-Jung Chen, Tsung-Hsien Tsai, Liang-Kung Chen, Shih-Tsung Huang, Fei-Yuan Hsiao
  • Publication number: 20220209093
    Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.
    Type: Application
    Filed: January 7, 2022
    Publication date: June 30, 2022
    Inventors: Ming-Hsien TSAI, Shang-Ying TSAI, Fu-Lung HSUEH, Shih-Ming YANG, Jheng-Yuan WANG, Ming-De CHEN
  • Publication number: 20220173288
    Abstract: A light source assembly is provided, including a substrate; a light-emitting element disposed on the substrate; and an optical film at least partially overlapped with the substrate. A diffuser film is at least partially overlapped with the optical film, wherein a haze of the diffuser film is greater than 85%, and a thickness of the diffuser film ranges from 0.04 mm to 0.35 mm. The optical film and the diffuser film are capable of transmitting at least a part of light emitted from the light-emitting element.
    Type: Application
    Filed: February 16, 2022
    Publication date: June 2, 2022
    Inventors: Chia-Lun CHEN, Shih-Chang HUANG, Ming-Hui CHU, Chih-Chang CHEN, Kai-Hsien HSIUNG, Hui-Chi WANG, Wun-Yuan SU
  • Publication number: 20220147691
    Abstract: A method includes the following operations: receiving design rule violations of a first layout; classifying, according to first chip features of the first layout, a first violation of the design rule violations into a first class of predefined classes; generating a first vector array for at least one of the first chip features of the first layout, that is associated with the first violation; selecting, according to the first vector array, first operations from pre-stored operations; generating a second layout based on the first layout and the first operations.
    Type: Application
    Filed: December 8, 2020
    Publication date: May 12, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPNAY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Yi-Lin CHUANG, Song LIU, Pei-Pei CHEN, Heng-Yi LIN, Shih-Yao LIN, Chin-Hsien WANG
  • Patent number: 11152383
    Abstract: A memory cell may include first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Publication number: 20210280592
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region, second well region, and third well region disposed within a substrate. The second well region is laterally between the first and third well regions. An isolation structure is disposed within the substrate and laterally surrounds the first, second, and third well regions. A floating gate overlies the substrate and laterally extends from the first well region to the third well region. A dielectric structure is disposed under the floating gate. A bit line write region is disposed within the second well region and comprises source/drain regions disposed on opposite sides of the floating gate. A bit line read region is disposed within the second well region, is laterally offset from the bit line write region by a non-zero distance, and comprises source/drain regions disposed on the opposite sides of the floating gate.
    Type: Application
    Filed: October 13, 2020
    Publication date: September 9, 2021
    Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Publication number: 20210280591
    Abstract: Various embodiments of the present disclosure are directed towards a memory cell including first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 9, 2021
    Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Publication number: 20210137669
    Abstract: A polymer fiber tubular structure includes a first pipe element, a second pipe element, and a coil winding structure, wherein the first pipe element includes an inner surface and an outer surface and is composed of silicon-containing polycarbonate type polyurethane elastomer, the second pipe element includes an inner surface and an outer surface and is composed of polycarbonate type polyurethane elastomer. The second pipe element is wrapped on the outer surface of the first pipe element such that the first pipe element and the second pipe element are concentric structures. The coil winding structure is provided for embedding into the outer surface of the first pipe element or into the outer surface of the second pipe element, thereby, the kinking of the polymer fiber tubular structure is to be reduced during use, and the thrombosis can be further avoided when the polymer fiber tubular is used for the human being.
    Type: Application
    Filed: April 10, 2020
    Publication date: May 13, 2021
    Inventors: Shih-Hsien Chen, Cin-He Chang, Yung-Tai Lin
  • Publication number: 20210082839
    Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang
  • Patent number: 10892235
    Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang
  • Patent number: 10784276
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Patent number: 10727222
    Abstract: A memory system is provided. The memory system includes a number of memory cells and a number of bit lines. The memory cells are interlocked with each other in rows and columns. The memory cells include respective capacitors, respective first transistors and respective second transistors. Respective upper plates of the respective capacitors are electrically connected to respective gates of the respective first transistors, and respective drains of the respective second transistors are connected to respective sources of the respective first transistors. The bit lines are arranged along an extending direction of the rows. Respective bit lines are connected to the respective first transistors through respective bit-line contacts, and each of the respective bit-line contacts is shared by two adjacent memory cells of the extending direction of the rows.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Publication number: 20200066657
    Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.
    Type: Application
    Filed: September 19, 2018
    Publication date: February 27, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang
  • Patent number: 10553597
    Abstract: A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hsien Chen, Liang-Tai Kuo, Hau-Yan Lu, Chun-Yao Ko
  • Patent number: 10438893
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a first metal interconnection and a second metal interconnection in the first IMD layer; removing part of the first IMD layer to form a recess between the first metal interconnection and the second metal interconnection; performing a curing process; and forming a second IMD layer on the first metal interconnection and the second metal interconnection.
    Type: Grant
    Filed: October 15, 2017
    Date of Patent: October 8, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hsien Chen, Meng-Jun Wang, Ting-Chun Wang, Chih-Sheng Chang
  • Publication number: 20190131312
    Abstract: A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.
    Type: Application
    Filed: December 24, 2018
    Publication date: May 2, 2019
    Inventors: Shih-Hsien CHEN, Liang-Tai KUO, Hau-Yan LU, Chun-Yao KO
  • Publication number: 20190096903
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 28, 2019
    Inventors: Hau-Yan LU, Shih-Hsien CHEN, Chun-Yao KO, Felix Ying-Kit TSUI
  • Publication number: 20190096819
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a first metal interconnection and a second metal interconnection in the first IMD layer; removing part of the first IMD layer to form a recess between the first metal interconnection and the second metal interconnection; performing a curing process; and forming a second IMD layer on the first metal interconnection and the second metal interconnection.
    Type: Application
    Filed: October 15, 2017
    Publication date: March 28, 2019
    Inventors: Shih-Hsien Chen, Meng-Jun Wang, Ting-Chun Wang, Chih-Sheng Chang
  • Patent number: 10163920
    Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hsien Chen, Liang-Tai Kuo, Hau-Yan Lu, Chun-Yao Ko
  • Patent number: 10141323
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui