Patents by Inventor Shih Hsien Huang
Shih Hsien Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955536Abstract: A semiconductor transistor structure includes a substrate with a first conductivity type, a fin structure grown on the substrate, and a gate on the fin structure. The fin structure includes a first epitaxial layer having a second conductivity type opposite to the first conductivity type, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer having the second conductivity type on the second epitaxial layer.Type: GrantFiled: July 15, 2021Date of Patent: April 9, 2024Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, Wen Yi Tan
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11930157Abstract: The disclosure provides an eye tracking method and an eye tracking device. The method includes obtaining a reference interpupillary distance value; taking images of a user of a 3D display, and finding a first eye pixel coordinate corresponding to a first eye of the user and a second eye pixel coordinate corresponding to a second eye of the user in each image; detecting a first and a second eye spatial coordinates of the first and the second eyes, and determining projection coordinates based on the first eye spatial coordinate, the second eye spatial coordinate, and optical parameters of image capturing elements; determining an optimization condition related to the first and second eye spatial coordinates based on the first and second eye pixel coordinates, the projection coordinates, and the reference interpupillary distance value of each image; and optimizing the first and second eye spatial coordinates based on the optimization condition.Type: GrantFiled: March 29, 2022Date of Patent: March 12, 2024Assignee: Acer IncorporatedInventors: Yen-Hsien Li, Shih-Ting Huang, Chao-Shih Huang
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Patent number: 11923200Abstract: An integrated circuit includes a gate structure over a substrate. The integrated circuit includes a first silicon-containing material structure in a recess. The first silicon-containing material structure includes a first layer below a top surface of the substrate and in direct contact with the substrate. The first silicon-containing material structure includes a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure is thinner than a second region of the second layer farther from the gate structure. The first silicon-containing material structure includes a third layer between the first layer and the second layer, wherein at least a portion of the third layer is below the top surface of the substrate.Type: GrantFiled: May 25, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hsien Huang, Yi-Fang Pai, Chien-Chang Su
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Publication number: 20240030295Abstract: The invention provides a semiconductor manufacturing method, which comprises providing a substrate, forming a silicon germanium epitaxial layer in the substrate, forming a first silicon layer on the silicon germanium epitaxial layer, wherein the first silicon layer is a pure silicon layer, and forming a second silicon layer on the first silicon layer, wherein the second silicon layer comprises a silicon layer doped with boron atoms.Type: ApplicationFiled: August 16, 2022Publication date: January 25, 2024Applicant: United Semiconductor (Xiamen) Co., Ltd.Inventors: YONG XIE, QIANG GAO, Shih-Hsien Huang, WEN YI TAN
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Publication number: 20230402444Abstract: An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction. The IC structure also includes a first standard cell including a first metal gate stack engaged with the first portion, a second standard cell including a second metal gate stack engaged with the second portion, and a filler cell disposed between the first standard cell and the second standard cell, where the filler cell includes the third portion that connects the first portion to the second portion.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Inventors: Shih-Hsien Huang, Cheng-Hua Liu, Kuang-Hung Chang, Sheng-Hsiung Wang, Chun-Yen Lin, TUNG-HENG HSIEH, BAO-RU Young
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Publication number: 20230317453Abstract: A method of removing a hard mask layer includes providing a gate. A hard mask layer covers and contacts a top surface of the gate. Two spacer structures respectively contacts two sides of the gate. Two first spacers are respectively disposed on the two spacer structures. Later, a wet etching process is performed to remove the hard mask layer and the first spacers and keep the spacer structures. An etchant is utilized in the wet etching process. A selective etching ratio of the silicon nitride to silicon oxide of the etchant is more than 90. The etchant includes Si(OH)4. A concentration of Si(OH)4.is greater than or equal to 3.95 ppm and smaller than or equal to 10 ppm.Type: ApplicationFiled: April 6, 2022Publication date: October 5, 2023Applicant: United Semiconductor (Xiamen) Co., Ltd.Inventors: Sen Mao Feng, Ming Xuan Ren, Shih-Hsien Huang, Wen Yi TAN
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Publication number: 20230298891Abstract: A method includes selectively etching a region of a substrate using a germanium-containing gas, wherein the region of the substrate consists of Si and another material, and the other material consists of SiGe. The method further includes wherein the region has a laminated structure having a SiGe film over a Si film.Type: ApplicationFiled: May 24, 2023Publication date: September 21, 2023Inventors: Shih-Hsien HUANG, Yi-Fang PAI, Chien-Chang SU
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Publication number: 20230260900Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.Type: ApplicationFiled: April 28, 2023Publication date: August 17, 2023Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Fu-Kai Yang, Mei-Yun Wang, Sheng-Hsiung Wang, Shih-Hsien Huang
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Publication number: 20230253500Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Huang-Siang LAN, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh WONG, Hung-Yu YEH, Chung-En TSAI
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Publication number: 20230246090Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Applicant: United Semiconductor (Xiamen) Co., Ltd.Inventors: Shih-Hsien Huang, Sheng-Hsu Liu, Wen Yi Tan
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Patent number: 11658229Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.Type: GrantFiled: June 29, 2020Date of Patent: May 23, 2023Inventors: Shih-Hsien Huang, Sheng-Hsu Liu, Wen Yi Tan
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Publication number: 20230138009Abstract: A method for forming a semiconductor structure includes forming a gate structure on a substrate, performing a deposition process to form a nitride layer to cover the substrate and the gate structure, performing an in-situ annealing process to the nitride layer, and performing an anisotropic etching process to the nitride layer after the in-situ annealing process to form a spacer on a sidewall of the gate structure.Type: ApplicationFiled: December 22, 2021Publication date: May 4, 2023Applicant: United Semiconductor (Xiamen) Co., Ltd.Inventors: Jun Wu, Shih-Hsien Huang, WEN YI TAN, FENG GAO
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Patent number: 11640936Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.Type: GrantFiled: January 8, 2021Date of Patent: May 2, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Fu-Kai Yang, Mei-Yun Wang, Sheng-Hsiung Wang, Shih-Hsien Huang
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Patent number: 11637183Abstract: A method for fabricating a semiconductor transistor is disclosed. A substrate of a first conductivity type is provided. An ion well of a second conductivity type is formed in the substrate. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate. A gate dielectric layer is formed on the epitaxial channel layer. A gate is formed on the gate dielectric layer. A source region and a drain region are then formed in the substrate. The source region and the drain region have the first conductivity type.Type: GrantFiled: February 14, 2022Date of Patent: April 25, 2023Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, Wen Yi Tan
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Patent number: 11631768Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.Type: GrantFiled: July 1, 2019Date of Patent: April 18, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai
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Publication number: 20220399459Abstract: A semiconductor transistor structure includes a substrate with a first conductivity type, a fin structure grown on the substrate, and a gate on the fin structure. The fin structure includes a first epitaxial layer having a second conductivity type opposite to the first conductivity type, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer having the second conductivity type on the second epitaxial layer.Type: ApplicationFiled: July 15, 2021Publication date: December 15, 2022Applicant: United Semiconductor (Xiamen) Co., Ltd.Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, WEN YI TAN
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Publication number: 20220367538Abstract: Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Yueh-Chuan LEE, Shih-Hsien HUANG, Chia-Chan CHEN, Pu-Fang CHEN
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Publication number: 20220285157Abstract: An integrated circuit includes a gate structure over a substrate. The integrated circuit includes a first silicon-containing material structure in a recess. The first silicon-containing material structure includes a first layer below a top surface of the substrate and in direct contact with the substrate. The first silicon-containing material structure includes a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure is thinner than a second region of the second layer farther from the gate structure. The first silicon-containing material structure includes a third layer between the first layer and the second layer, wherein at least a portion of the third layer is below the top surface of the substrate.Type: ApplicationFiled: May 25, 2022Publication date: September 8, 2022Inventors: Shih-Hsien HUANG, Yi-Fang PAI, Chien-Chang SU
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Publication number: 20220223517Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.Type: ApplicationFiled: January 8, 2021Publication date: July 14, 2022Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Fu-Kai Yang, Mei-Yun Wang, Sheng-Hsiung Wang, Shih-Hsien Huang