Abstract: The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

Abstract: A semiconductor capacitor array layout generates parasitic capacitance toward an edge of the layout to reduce a capacitance difference between an outer capacitor unit and an inner capacitor unit. The semiconductor capacitor array layout includes a primary capacitor structure and an outer capacitor structure. Each of the primary capacitor structure and the outer capacitor structure includes a first crisscross structure and a second crisscross structure that are staggered. Each of the first crisscross structure and the second crisscross structure includes longitudinal conductive strips and lateral conductive strips, wherein the longitudinal conductive strips are disposed in a first integrated circuit (IC) layer and the lateral conductive strips are disposed in a second IC layer. The second crisscross structure of the primary capacitor structure and the first crisscross structure of the outer capacitor structure jointly generate the parasitic capacitance.

Abstract: A comparator-based switched-capacitor circuit (SC circuit) has a first output terminal and a second output terminal, which output a first output signal and a second output signal, respectively. The comparator-based SC circuit includes a switch-capacitor network, a first current source, a second current source, and a compensation circuit. The first current source is coupled to the switch-capacitor network and the first output terminal. The second current source is coupled to the switch-capacitor network and the second output terminal. The compensation circuit is coupled to the first output terminal and the second output terminal and configured to generate a first and second voltage differences corresponding respectively to the first and second output signals and apply the first and second voltage differences to the second and first output terminals, respectively.

Abstract: The present application discloses a source follower circuit, arranged for generating output signal according to input signal. The circuit includes: a first transistor having a drain coupled to a first reference voltage; a second transistor having a drain coupled to a source of the first transistor, and the first transistor and the second transistor both have polarization of a first type; a first capacitor, coupled between a gate of the first transistor and the input signal; and a first resistor, coupled between the gate of the first transistor and a first bias voltage; wherein a gate of the second transistor is coupled to the input signal, and a source of the second transistor outputs the output signal.

Abstract: A comparator-based switched-capacitor circuit has a first output terminal and a second output terminal, and includes a switch-capacitor network, a first current source, and a second current source. Each of the first current source and the second current source includes a first transistor, a second transistor, a capacitor, and a buffer circuit. The first transistor has a first source, a first drain, and a first gate. The first drain is coupled to the first output terminal, the first source is coupled to a reference voltage, and the first gate is coupled to the switch-capacitor network. The second transistor has a second source, a second drain, and a second gate. The second source is coupled to the first output terminal. The capacitor is coupled between the second gate and the second source. The buffer circuit is coupled between the second source and the second drain.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism is provided. A digital-to-analog conversion circuit includes conversion circuits to generate an output analog signal and echo-canceling analog signals. An echo transmission circuit processes an echo-transmitting path to generate an echo signal. An echo calibration circuit generates an output calibration signal and echo-canceling calibration signals according to an input digital circuit through calibration circuits corresponding to the conversion circuits. A calibration parameter calculating circuit generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signals and path information related to the echo calibration circuit.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having current source measuring mechanism. A digital-to-analog conversion circuit in turn sets one of thermo-controlled current sources as an initial current source to operate according to two specific input codewords included in an input digital signal to generate an output analog signal. The values of the output analog signal corresponding to the two specific input codewords have opposite signs and the same absolute value. An echo transmission circuit processes the output analog signal to generate an echo signal. An echo-canceling circuit processes the input digital signal according to echo-canceling coefficients to generate an echo-canceling signal and receives an error signal to converge the echo-canceling coefficients.

Abstract: A comparator-based switched-capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes an analog-to-digital converter (ADC), a decoder, and a switch-capacitor network. The ADC is coupled to the first input terminal and the second input terminal and includes a plurality of comparators. The decoder is coupled to the ADC. The switch-capacitor network includes a comparator, a first current source, a second current source, a plurality of switches, and a plurality of capacitors. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The voltage of the first output terminal and the voltage of the second output terminal do not exceed a target range.

Abstract: The present application discloses a source follower circuit, arranged for generating output signal according to input signal. The circuit includes: a first transistor having a drain coupled to a first reference voltage; a second transistor having a drain coupled to a source of the first transistor, and the first transistor and the second transistor both have polarization of a first type; a first capacitor, wherein a terminal of the first capacitor selectively coupled to the input signal or a gate of the first transistor, another terminal of the first capacitor selectively coupled to a second reference voltage or a first bias; a second capacitor, wherein a terminal of the second capacitor selectively coupled to the input signal or a gate of the second transistor, another terminal of the second capacitor selectively coupled to a third reference voltage or a second bias.

Abstract: A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into a plurality of first digital codes, in which a first converter circuitry in the converter circuitries is configured to perform a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate control signals, and determines whether to set the second digital code to be a second corresponding digital code in predetermined digital codes according to the control signals.

Abstract: The present disclosure discloses a switched capacitor amplifier apparatus for improving level-shifting. An amplifier includes input terminals and output terminals. Two capacitor circuits correspond to signal input terminals and signal output terminals and each includes a sampling capacitor circuit, a load capacitor and a level-shifting capacitor. The sampling capacitor circuit samples an input signal from one of the signal input terminals to one of the input terminals. An electrical charge neutralizing capacitor is coupled between the output terminals. The load capacitor and the level-shifting capacitor are charged according to an output from one of the output terminals in an estimation period. The level-shifting capacitor charges the load capacitor in a level-shifting period to generate an output signal at one of the signal output terminals.

Abstract: The present application discloses an amplifier and a method for controlling a common mode voltage thereof. The method includes: generating a control signal according to a positive-terminal input signal, a negative-terminal input signal and a target common mode voltage; and coupling the controlling signal to a first terminal of a positive-terminal capacitor and a first terminal of a negative-terminal capacitor, to adjust degree of conduction of a positive-terminal p-type transistor and degree of conduction of a negative-terminal p-type transistor, or to adjust degree of conduction of a positive-terminal n-type transistor and degree of conduction of a negative-terminal n-type transistor, thereby changing a common mode voltage.

Abstract: The application discloses a circuit, including: a positive-terminal p-type transistor; a negative-terminal p-type transistor; a positive-terminal n-type transistor, wherein the positive-terminal p-type transistor and the positive-terminal n-type transistor are cascoded between a first reference voltage and a second reference voltage; a negative-terminal n-type transistor, wherein the negative-terminal p-type transistor and the negative-terminal n-type transistor are cascoded between the first reference voltage and the second reference voltage; a first positive-terminal capacitor, a top plate of the first positive-terminal capacitor is coupled to a gate of the positive-terminal n-type transistor; a first negative-terminal capacitor, a top plate of the first negative-terminal capacitor is coupled to a gate of the negative-terminal n-type transistor; a first control circuit, arranged to generate a first control signal to bottom plates of the first positive-terminal capacitor and the first negative-terminal capac

Abstract: The present invention discloses an analog-to-digital conversion circuit having remained time measuring mechanism is provided. A digital-to-analog conversion (DAC) circuit samples input voltages to generate output voltages. A comparator compares the output voltages to generate a comparison result. A control circuit switches a configuration of the DAC circuit by using a digital code according to the comparison result. A comparison determining circuit sets a stage indication signal at a finished state after the comparison result is generated. A comparison stage counting circuit accumulates a termination number according to the stage indication signal to set a conversion indication signal at the finished state when the termination number reaches a predetermined number. A time accumulating circuit starts to accumulate a remained time when the conversion indication signal is at the finished state and finishes accumulation when a sampling indication signal is at a sampling state.

Abstract: The present invention discloses a comparison circuit having adaptive comparison mechanism is provided. A comparator is enabled by an enabling signal having an enabling state during a comparison stage to compare a first voltage and a second voltage to generate a comparison result. A comparison determining circuit sets a stage indication signal at an unfinished state and a finished state before and after the comparison result is generated. A time accumulating circuit starts to accumulate an accumulated time when the enabling signal is at the enabling state and stops accumulating when the stage indication signal is at the finished state to generate a comparison time. A determining circuit performs statistics on the comparison time to generate a predetermined threshold time and sets a predetermined comparison result as the comparison result under the condition that the comparison result is not generated and the accumulated time exceeds the predetermined threshold time.

Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism. A DAC circuit includes conversion circuits to generate an output analog signal and an echo-canceling analog signal. An echo transmission circuit performs signal processing on an echo path to generate an echo signal. An echo calibration circuit includes odd and even calibration circuits to perform mapping according to offset tables and perform processing according to response coefficients on odd and even input parts of an input digital signal to generate odd and even calibration parts of an echo-canceling calibration signal. A calibration parameter calculation circuit generates offsets according to an error signal between the echo signal and the echo-canceling calibration signal and path information related to the echo calibration circuit.

Abstract: An analog-to-digital converter, configured to convert an input signal into an n bits digital output signal, includes a capacitor module, a control signal generation unit, a comparator, and a register. The capacitor module is configured to receive the input signal at a sampling phase in a normal mode, and to generate a first sampling signal and a second sampling signal according to the input signal in a conversion phase. The control signal generation unit is configured to adjust the first sampling signal or the second sampling signal in the conversion phase. In the normal mode, the comparator is configured to compare the first sampling signal and the second sampling signal in the conversion phase to generate n comparison signals. The register is configured to store the n comparison signals as the digital output signal, and output the digital output signal in the normal mode.

Abstract: A time-interleaved analog to digital converter includes coarse converter circuitries, a control logic circuit, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The coarse converter circuitries sequentially sample an input signal and perform coarse conversions to generate decision signals. The control logic circuit generates coarse digital codes according to the decision signals. The first and second transfer circuits respectively transfer first and second residue signals. The fine converter circuitry performs a fine conversion according to a corresponding first residue signal and a corresponding second residue signal to generate a fine digital code. A sampling interval for sampling the input signal and a coarse conversion interval for performing the coarse conversion are determined based on a fine conversion interval for performing the fine conversion.

Abstract: A front-end sampling circuit includes a global switch, a local switch, and an auxiliary switch. The global switch is configured to be selectively turned on according to a first control signal, in order to transmit an input signal. The local switch is configured to be selectively turned on according to a second control signal, in order to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal. The auxiliary switch is configured to be selectively turned on according to a third control signal, in order to transmit the input signal to the node, in which a turn-off time point of the auxiliary switch is set to be the same or earlier than a turn-off time point of the global switch.