Abstract: In a method of coating a photo resist over a wafer, dispensing the photo resist from a nozzle over the wafer is started while rotating the wafer, and dispensing the photo resist is stopped while rotating the wafer. After starting and before stopping the dispensing the photo resist, a wafer rotation speed is changed at least 4 times. During dispensing, an arm holding the nozzle may move horizontally. A tip end of the nozzle may be located at a height of 2.5 mm to 3.5 mm from the wafer.

Abstract: Disclosed is an electronic device including a device body and an antenna module. The antenna module includes a conductive element and at least one antenna element. The conductive element includes a main body portion and at least one assembly portion connected with each other. The at least one assembly portion is assembled on the device body. The at least one antenna element is disposed on the device body and coupled with the conductive element to excite a first resonance mode. The at least one assembly portion overlaps the at least one antenna element in the length direction of the main body portion.

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: An active stylus having physical writing function includes a tip shell including a first opening and a second opening, a first electrode including a first end protruded through the first opening of the tip shell and including a second end protruded through the second opening of the tip shell and entered a main body housing of the active stylus, wherein the first electrode includes conductive material. The tip shell includes non-conductive material. The first end of the first electrode is configured to leave colored traces on an object by physical friction caused between the first end of the first electrode and the object.

Abstract: A photodetector includes a first semiconductor layer, an absorption structure, a second semiconductor layer, and a barrier structure. The absorption structure is located on the first semiconductor layer, and having a first conduction band, a first valence band, and a first band gap. The second semiconductor layer is located on the absorption structure, and having a second conduction band, a second valence band, and a second band gap. The barrier structure is located between the absorption structure and the second semiconductor layer, and having a third conduction band, a third valence band, and a third band gap. The third conduction band is greater than the second conduction band or the third valence band is less than the second valence band.

Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.

Abstract: A method for cleaning a substrate includes the following: exposing the substrate to a cleaning agent to remove impurities on a surface of the substrate; exposing the substrate to a dewetting chemical agent in a liquid phase to remove the cleaning agent on the surface of the substrate; solidifying the dewetting chemical agent in the liquid phase remaining on the surface of the substrate to obtain the dewetting chemical agent in a solid phase; and sublimating and removing the dewetting chemical agent in the solid phase.

Abstract: A method for cleaning a substrate includes the following: exposing the substrate to a cleaning agent to remove impurities on a surface of the substrate; exposing the substrate to a dewetting chemical agent in a liquid phase to remove the cleaning agent on the surface of the substrate; solidifying the dewetting chemical agent in the liquid phase remaining on the surface of the substrate to obtain the dewetting chemical agent in a solid phase; and sublimating and removing the dewetting chemical agent in the solid phase.

Abstract: The present application relates to a wafer processing device and a wafer processing method. The wafer processing device includes: a spraying unit configured to spray a photoresist-removing solution to remove a photoresist; and a heating unit mounted to the spraying unit and configured to heat the photoresist-removing solution to a preset temperature. According to the wafer processing device and wafer processing method of the present application, the photoresist-removing solution is heated to a preset temperature, so that the photoresist-removing solution dissolves the photoresist more rapidly and thoroughly. Therefore, the photoresist may be removed from a surface of the wafer more thoroughly, and further a yield of the wafer is increased.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof, including: providing a substrate and a plurality of discrete bit line structures, the bit line structures being located on the substrate, capacitor contact windows being provided between adjacent bit line structures; forming first isolation layers, the first isolation layers covering sidewalls of the bit line structures; forming a sacrificial layer, the sacrificial layer covering sidewalls of the first isolation layers; forming second isolation layers, the second isolation layers covering sidewalls of the sacrificial layer and exposing the top surfaces and bottoms of the sacrificial layer; etching the exposed bottoms of the sacrificial layer to form bottom gaps between the first isolation layers and the second isolation layers; etching the exposed top surfaces of the sacrificial layer to remove the remaining of the sacrificial layer so as to form gaps between the layers.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a memory device, and a semiconductor structure and a forming method thereof. The forming method includes: providing a substrate, where the substrate includes a source region and a drain region spaced apart from each other, and a gate trench located between the source region and the drain region; forming, in sequence on an inner wall of the gate trench, a gate oxide layer, an interface layer, and a conductive layer that fills the gate trench; and etching back the side of the interface layer away from the bottom of the gate trench by using a wet etching process, such that a top height of the interface layer is lower than a top height of the conductive layer.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming a patterned photoresist layer on the substrate, and etching the substrate by using the patterned photoresist layer as a mask; performing, by using a plasma asher, plasma ashing treatment on the patterned photoresist layer and residues produced by etching after the substrate is etched; and performing the plasma ashing treatment in an oxygen-free environment. According to the embodiments of the present application, residues on a semiconductor structure can be removed without producing new residues, thereby improving electrical properties of the semiconductor structure.

Abstract: An integrated fin antenna apparatus is provided. The integrated fin antenna apparatus comprises a base, a first antenna module, a second antenna module, a third antenna module and a housing. The first antenna module is disposed vertically on the base. The second antenna module is parallel to the first antenna module and disposed vertically on the base. The second antenna module is spaced from the first antenna module by substantial 10 mm. The third antenna module is disposed on and parallel to the base, wherein the third antenna module is disposed on one end of the base relative to the first antenna module and the second antenna module. The third antenna is parallel to the base. The housing is covering the base to form an accommodating space with the base. The accommodating space is used to accommodate the first antenna module, the second antenna module and the third antenna module.

Abstract: The embodiments disclose a lamp assembly structure that allows a plurality of lamp assemblies to form lamps of different configurations. The lamp assembly structure includes a plurality of independent block bodies, each block body has at least one convex connector or/and at least one concave connector. At least one block body has a luminous body. At least a part of the convex connector or/and the concave connector has an electrical connection component. The electrical connection component and the luminous body are connected electrically. When one block body and its adjacent block body are assembled together, the convex connector of one of the two block bodies is plugged into the concave connector of the other of the two block bodies so as to tightly combine the two block bodies. As a result the electrical connection components of the two block bodies are connected physically and electrically.

Abstract: The present application describes a vertical light-emitting diode (VLED) and its manufacture method that use the combination of a reflective layer, a transparent conducting layer and transparent dielectric layer as structural layers for promoting uniform current distribution and increasing light extraction. In the VLED, a transparent conducting layer is formed on a first outer surface of a stack of multiple group III nitride semiconductor layers. A transparent dielectric layer is then formed on a side of the transparent conducting layer opposite the side of the multi-layer structure. A first electrode structure is then formed on the transparent dielectric layer in electrical contact with the transparent conducting layer via a plurality of contact windows patterned through the transparent dielectric layer. The transparent conducting layer and the transparent dielectric layer are used as structural layers for improving light extraction.

Abstract: The embodiments disclose a lamp assembly structure that allows a plurality of lamp assemblies to form lamps of different configurations. The lamp assembly structure includes a plurality of independent block bodies, each block body has at least one convex connector or/and at least one concave connector. At least one block body has a luminous body. At least a part of the convex connector or/and the concave connector has an electrical connection component. The electrical connection component and the luminous body are connected electrically. When one block body and its adjacent block body are assembled together, the convex connector of one of the two block bodies is plugged into the concave connector of the other of the two block bodies so as to tightly combine the two block bodies. As a result the electrical connection components of the two block bodies are connected physically and electrically.

Abstract: In a method of manufacturing a vertical type light-emitting diode, a multilayered structure of group III nitride semiconductor compounds is epitaxy deposited on an irregular surface of a substrate. The substrate is then removed to expose an irregular surface of the multilayered structure corresponding to the irregular surface of the substrate. A portion of the exposed irregular surface of the multilayered structure is then etched for forming an electrode contact surface on which an electrode layer is subsequently formed. With this method, no specific planarized region is required on the irregular surface of the substrate. As a result, planarization treatment of the substrate is not necessary. The same substrate with the irregular surface can be reused for fabricating vertical and horizontal light-emitting diodes.

Abstract: The present application describes a vertical light-emitting diode (VLED) and its manufacture method that use the combination of a reflective layer, a transparent conducting layer and transparent dielectric layer as structural layers for promoting uniform current distribution and increasing light extraction. In the VLED, a transparent conducting layer is formed on a first outer surface of a stack of multiple group III nitride semiconductor layers. A transparent dielectric layer is then formed on a side of the transparent conducting layer opposite the side of the multi-layer structure. A first electrode structure is then formed on the transparent dielectric layer in electrical contact with the transparent conducting layer via a plurality of contact windows patterned through the transparent dielectric layer. The transparent conducting layer and the transparent dielectric layer are used as structural layers for improving light extraction.

Abstract: A method of indexing final pitching shots for each batter in a video recording of a baseball game is disclosed. The method includes locating pitching video frames in the video, identifying individual pitching shots contained in the video, determining which of the pitching shots is a final pitching shot for each batter in the baseball game, and creating an index of the final pitching shots.

Abstract: In a method of manufacturing a vertical type light-emitting diode, a multilayered structure of group III nitride semiconductor compounds is epitaxy deposited on an irregular surface of a substrate. The substrate is then removed to expose an irregular surface of the multilayered structure corresponding to the irregular surface of the substrate. A portion of the exposed irregular surface of the multilayered structure is then etched for forming an electrode contact surface on which an electrode layer is subsequently formed. With this method, no specific planarized region is required on the irregular surface of the substrate. As a result, planarization treatment of the substrate is not necessary. The same substrate with the irregular surface can be reused for fabricating vertical and horizontal light-emitting diodes.