Patents by Inventor Shih-Jia Zeng
Shih-Jia Zeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128987Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.Type: ApplicationFiled: November 28, 2022Publication date: April 18, 2024Applicant: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
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Patent number: 11962328Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.Type: GrantFiled: November 28, 2022Date of Patent: April 16, 2024Assignee: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
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Patent number: 11797222Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.Type: GrantFiled: January 17, 2022Date of Patent: October 24, 2023Assignee: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Po-Cheng Su, Chih-Wei Wang, Wei Lin
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Patent number: 11726709Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.Type: GrantFiled: August 17, 2020Date of Patent: August 15, 2023Assignee: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Yu-Siang Yang, Szu-Wei Chen, Wei Lin
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Publication number: 20230214150Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.Type: ApplicationFiled: February 24, 2022Publication date: July 6, 2023Applicant: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Chun-Wei Tsao, Hsiao-Yi Lin, Wei Lin
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Publication number: 20230195361Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.Type: ApplicationFiled: January 17, 2022Publication date: June 22, 2023Applicant: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Po-Cheng Su, Chih-Wei Wang, Wei Lin
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Publication number: 20220365706Abstract: A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.Type: ApplicationFiled: June 2, 2021Publication date: November 17, 2022Applicant: PHISON ELECTRONICS CORP.Inventors: Yu-Siang Yang, Wei Lin, Shih-Jia Zeng, An-Cheng Liu, Yu-Cheng Hsu
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Patent number: 11373713Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: reading multiple first memory cells using multiple read voltage levels to obtain a first threshold voltage distribution of the first memory cells; obtaining shift information of the first threshold voltage distribution with respect to an original threshold voltage distribution of the first memory cells; obtaining first reliability information corresponding to the first threshold voltage distribution; recovering original reliability information corresponding to the original threshold voltage distribution according to a statistical characteristic of the first reliability information; adjusting the original reliability information according to the shift information to obtain second reliability information corresponding to the first threshold voltage distribution; and updating reliability information related to the first memory cells according to the second reliability information.Type: GrantFiled: March 22, 2021Date of Patent: June 28, 2022Assignee: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Lih Yuarn Ou, Hsiao-Yi Lin, Wei Lin
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Publication number: 20220107756Abstract: An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.Type: ApplicationFiled: October 27, 2020Publication date: April 7, 2022Applicant: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Chun-Wei Tsao, Chih-Wei Wang, Wei Lin
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Publication number: 20220027089Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.Type: ApplicationFiled: August 17, 2020Publication date: January 27, 2022Applicant: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Yu-Siang Yang, Szu-Wei Chen, Wei Lin
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Publication number: 20210334684Abstract: A method of building a decoding status prediction system is provided. Firstly, plural read records are collected during read cycles of a flash memory. Then, the plural read records are classified into read records with a first read result and read records with a second read result. Then, a first portion of the read records with the first read result are divided into K0 groups according to a clustering algorithm, and a second portion of the read records with the second read result are divided into K1 groups according to the clustering algorithm. Then, the read records of the K0 groups and the K1 groups are used to train prediction models. Consequently, K0×K1 prediction models are generated. Then, the prediction models are combined as a prediction database.Type: ApplicationFiled: July 2, 2021Publication date: October 28, 2021Inventors: Yen-Chin LIAO, Ching-Hui HUANG, Shih-Jia ZENG, Hsie-Chia CHANG
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Patent number: 11101820Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: sending a first read command sequence which indicates a reading of a first physical unit by using a first read voltage level to obtain first data; decoding the first data; sending a second read command sequence which indicates a reading of the first physical unit by using a second read voltage level to obtain second data; decoding the second data with assistance information to improve a decoding success rate of the second data if the second read voltage level meets a first condition or the second data meets a second condition; and decoding the second data without the assistance information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.Type: GrantFiled: June 2, 2020Date of Patent: August 24, 2021Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Shih-Jia Zeng, Yu-Cheng Hsu, Yu-Siang Yang
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Patent number: 10802913Abstract: A solid state storage device using a prediction function is provided. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit generates collection read operation commands. The collection read operation commands are temporarily stored in a command queue, and transmitted to the non-volatile memory. According to each of the collection read operation commands, the non-volatile memory generates a corresponding encoded read data to the control circuit. After the error correction circuit performs a decoding operation on the encoded read data, a decoded content is generated and a first count of the decoded content is transmitted to a first register of the register set. After the encoded read data is decoded, a value stored in the first register is a first parameter and the first parameter is inputted into a prediction function of the function storage circuit.Type: GrantFiled: July 25, 2019Date of Patent: October 13, 2020Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATIONInventors: Shih-Jia Zeng, Tsu-Han Lu, Hsiao-Chang Yen
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Patent number: 10720222Abstract: A solid state storage device includes a non-volatile memory and a control circuit. The non-volatile memory includes a specified region. The control circuit is connected with the non-volatile memory, and includes a function storage circuit. A state prediction function for a first failure mode and a state prediction function for a second failure mode are stored in the function storage circuit. If the control circuit confirms that the specified region is changed from the first failure mode to the second failure mode, the control circuit predicts the specified region according to current state parameters of the specified region and the state prediction function for the second failure mode.Type: GrantFiled: October 11, 2018Date of Patent: July 21, 2020Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATIONInventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Hsiao-Chang Yen
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Patent number: 10658065Abstract: A failure mode detection method is provided. A first default read voltage is changed to a first read retry voltage by a first increment, and a second default read voltage is changed to a second read retry voltage by a second increment. A memory cell array of a solid state storage device is successfully read according to the first and second read retry voltages. If an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, the memory cell array is in a data retention failure mode. If the absolute value of the first increment minus the absolute value of the second increment is smaller than the predetermined voltage value, the memory cell array is in a low temperature write high temperature read failure mode.Type: GrantFiled: April 18, 2018Date of Patent: May 19, 2020Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATIONInventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Kuan-Chun Chen
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Patent number: 10629289Abstract: A solid state storage device is in communication with a host. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit is in communication with the host. The control circuit includes an error correction circuit and a prediction model storage circuit. A prediction model is stored in the prediction model storage circuit. The non-volatile memory includes a memory cell array. The memory cell array includes plural blocks. Each of the blocks includes a corresponding state parameter. The control circuit determines a selected block from the memory cell array. The control circuit judges whether to perform a specified operation on the selected block according to the state parameter of the selected block and the prediction model.Type: GrantFiled: June 21, 2018Date of Patent: April 21, 2020Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATIONInventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Kuan-Chun Chen
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Patent number: 10629269Abstract: A read table management method for a solid state storage device includes the following steps. If the lowest computation value in a hot group is lower than the highest computation value in a cold group when a read table adjusting process is enabled, a first read voltage set corresponding to the lowest computation value in the hot group and a second read voltage set corresponding to the highest computation value in the cold group are swapped with each other. Consequently, the second read voltage set becomes to belong to the hot group, and the first read voltage set becomes to belong to the cold group.Type: GrantFiled: September 19, 2018Date of Patent: April 21, 2020Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATIONInventors: Shih-Jia Zeng, Chun-Wei Kuo, Kuan-Chun Chen, Jen-Chien Fu
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Patent number: 10606518Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.Type: GrantFiled: October 19, 2018Date of Patent: March 31, 2020Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATIONInventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Hsiao-Chang Yen
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Publication number: 20200065174Abstract: A solid state storage device includes a non-volatile memory and a control circuit. The non-volatile memory includes a specified region. The control circuit is connected with the non-volatile memory, and includes a function storage circuit. A state prediction function for a first failure mode and a state prediction function for a second failure mode are stored in the function storage circuit. If the control circuit confirms that the specified region is changed from the first failure mode to the second failure mode, the control circuit predicts the specified region according to current state parameters of the specified region and the state prediction function for the second failure mode.Type: ApplicationFiled: October 11, 2018Publication date: February 27, 2020Inventors: Shih-Jia ZENG, Jen-Chien FU, Tsu-Han LU, Hsiao-Chang YEN
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Publication number: 20200042237Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.Type: ApplicationFiled: October 19, 2018Publication date: February 6, 2020Inventors: Shih-Jia ZENG, Jen-Chien FU, Tsu-Han LU, Hsiao-Chang YEN