Patents by Inventor Shih-Jia Zeng

Shih-Jia Zeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11373713
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: reading multiple first memory cells using multiple read voltage levels to obtain a first threshold voltage distribution of the first memory cells; obtaining shift information of the first threshold voltage distribution with respect to an original threshold voltage distribution of the first memory cells; obtaining first reliability information corresponding to the first threshold voltage distribution; recovering original reliability information corresponding to the original threshold voltage distribution according to a statistical characteristic of the first reliability information; adjusting the original reliability information according to the shift information to obtain second reliability information corresponding to the first threshold voltage distribution; and updating reliability information related to the first memory cells according to the second reliability information.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: June 28, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Lih Yuarn Ou, Hsiao-Yi Lin, Wei Lin
  • Publication number: 20220107756
    Abstract: An exemplary embodiment of the invention provides a read voltage control method for a rewritable non-volatile memory module. The method includes: sending a first read command sequence which instructs a reading of a plurality of first memory cells by using a first voltage level to obtain first data; obtaining first adjustment information of a read voltage according to the first data and a channel parameter of the first memory cells, and the channel parameter reflects a channel status of the first memory cells; and adjusting a voltage level of the read voltage from the first voltage level to a second voltage level according to the first adjustment information.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 7, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Chun-Wei Tsao, Chih-Wei Wang, Wei Lin
  • Publication number: 20220027089
    Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.
    Type: Application
    Filed: August 17, 2020
    Publication date: January 27, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Yu-Siang Yang, Szu-Wei Chen, Wei Lin
  • Publication number: 20210334684
    Abstract: A method of building a decoding status prediction system is provided. Firstly, plural read records are collected during read cycles of a flash memory. Then, the plural read records are classified into read records with a first read result and read records with a second read result. Then, a first portion of the read records with the first read result are divided into K0 groups according to a clustering algorithm, and a second portion of the read records with the second read result are divided into K1 groups according to the clustering algorithm. Then, the read records of the K0 groups and the K1 groups are used to train prediction models. Consequently, K0×K1 prediction models are generated. Then, the prediction models are combined as a prediction database.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 28, 2021
    Inventors: Yen-Chin LIAO, Ching-Hui HUANG, Shih-Jia ZENG, Hsie-Chia CHANG
  • Patent number: 11101820
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: sending a first read command sequence which indicates a reading of a first physical unit by using a first read voltage level to obtain first data; decoding the first data; sending a second read command sequence which indicates a reading of the first physical unit by using a second read voltage level to obtain second data; decoding the second data with assistance information to improve a decoding success rate of the second data if the second read voltage level meets a first condition or the second data meets a second condition; and decoding the second data without the assistance information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 24, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Shih-Jia Zeng, Yu-Cheng Hsu, Yu-Siang Yang
  • Patent number: 10802913
    Abstract: A solid state storage device using a prediction function is provided. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit generates collection read operation commands. The collection read operation commands are temporarily stored in a command queue, and transmitted to the non-volatile memory. According to each of the collection read operation commands, the non-volatile memory generates a corresponding encoded read data to the control circuit. After the error correction circuit performs a decoding operation on the encoded read data, a decoded content is generated and a first count of the decoded content is transmitted to a first register of the register set. After the encoded read data is decoded, a value stored in the first register is a first parameter and the first parameter is inputted into a prediction function of the function storage circuit.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 13, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Tsu-Han Lu, Hsiao-Chang Yen
  • Patent number: 10720222
    Abstract: A solid state storage device includes a non-volatile memory and a control circuit. The non-volatile memory includes a specified region. The control circuit is connected with the non-volatile memory, and includes a function storage circuit. A state prediction function for a first failure mode and a state prediction function for a second failure mode are stored in the function storage circuit. If the control circuit confirms that the specified region is changed from the first failure mode to the second failure mode, the control circuit predicts the specified region according to current state parameters of the specified region and the state prediction function for the second failure mode.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 21, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Hsiao-Chang Yen
  • Patent number: 10658065
    Abstract: A failure mode detection method is provided. A first default read voltage is changed to a first read retry voltage by a first increment, and a second default read voltage is changed to a second read retry voltage by a second increment. A memory cell array of a solid state storage device is successfully read according to the first and second read retry voltages. If an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, the memory cell array is in a data retention failure mode. If the absolute value of the first increment minus the absolute value of the second increment is smaller than the predetermined voltage value, the memory cell array is in a low temperature write high temperature read failure mode.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 19, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Kuan-Chun Chen
  • Patent number: 10629269
    Abstract: A read table management method for a solid state storage device includes the following steps. If the lowest computation value in a hot group is lower than the highest computation value in a cold group when a read table adjusting process is enabled, a first read voltage set corresponding to the lowest computation value in the hot group and a second read voltage set corresponding to the highest computation value in the cold group are swapped with each other. Consequently, the second read voltage set becomes to belong to the hot group, and the first read voltage set becomes to belong to the cold group.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 21, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Chun-Wei Kuo, Kuan-Chun Chen, Jen-Chien Fu
  • Patent number: 10629289
    Abstract: A solid state storage device is in communication with a host. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit is in communication with the host. The control circuit includes an error correction circuit and a prediction model storage circuit. A prediction model is stored in the prediction model storage circuit. The non-volatile memory includes a memory cell array. The memory cell array includes plural blocks. Each of the blocks includes a corresponding state parameter. The control circuit determines a selected block from the memory cell array. The control circuit judges whether to perform a specified operation on the selected block according to the state parameter of the selected block and the prediction model.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 21, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Kuan-Chun Chen
  • Patent number: 10606518
    Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: March 31, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Hsiao-Chang Yen
  • Publication number: 20200065174
    Abstract: A solid state storage device includes a non-volatile memory and a control circuit. The non-volatile memory includes a specified region. The control circuit is connected with the non-volatile memory, and includes a function storage circuit. A state prediction function for a first failure mode and a state prediction function for a second failure mode are stored in the function storage circuit. If the control circuit confirms that the specified region is changed from the first failure mode to the second failure mode, the control circuit predicts the specified region according to current state parameters of the specified region and the state prediction function for the second failure mode.
    Type: Application
    Filed: October 11, 2018
    Publication date: February 27, 2020
    Inventors: Shih-Jia ZENG, Jen-Chien FU, Tsu-Han LU, Hsiao-Chang YEN
  • Publication number: 20200042237
    Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.
    Type: Application
    Filed: October 19, 2018
    Publication date: February 6, 2020
    Inventors: Shih-Jia ZENG, Jen-Chien FU, Tsu-Han LU, Hsiao-Chang YEN
  • Publication number: 20200035307
    Abstract: A read table management method for a solid state storage device includes the following steps. If the lowest computation value in a hot group is lower than the highest computation value in a cold group when a read table adjusting process is enabled, a first read voltage set corresponding to the lowest computation value in the hot group and a second read voltage set corresponding to the highest computation value in the cold group are swapped with each other. Consequently, the second read voltage set becomes to belong to the hot group, and the first read voltage set becomes to belong to the cold group.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 30, 2020
    Inventors: Shih-Jia ZENG, Chun-Wei KUO, Kuan-Chun CHEN, Jen-Chien FU
  • Publication number: 20190348143
    Abstract: A solid state storage device is in communication with a host. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit is in communication with the host. The control circuit includes an error correction circuit and a prediction model storage circuit. A prediction model is stored in the prediction model storage circuit. The non-volatile memory includes a memory cell array. The memory cell array includes plural blocks. Each of the blocks includes a corresponding state parameter. The control circuit determines a selected block from the memory cell array. The control circuit judges whether to perform a specified operation on the selected block according to the state parameter of the selected block and the prediction model.
    Type: Application
    Filed: June 21, 2018
    Publication date: November 14, 2019
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Kuan-Chun Chen
  • Publication number: 20190279735
    Abstract: A failure mode detection method is provided. A first default read voltage is changed to a first read retry voltage by a first increment, and a second default read voltage is changed to a second read retry voltage by a second increment. A memory cell array of a solid state storage device is successfully read according to the first and second read retry voltages. If an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, the memory cell array is in a data retention failure mode. If the absolute value of the first increment minus the absolute value of the second increment is smaller than the predetermined voltage value, the memory cell array is in a low temperature write high temperature read failure mode.
    Type: Application
    Filed: April 18, 2018
    Publication date: September 12, 2019
    Inventors: Shih-Jia ZENG, Jen-Chien Fu, Tsu-Han Lu, Kuan-Chun Chen
  • Patent number: 10403379
    Abstract: An erased block reverification method for a solid state storage device is provided. Firstly, an erase command corresponding to a selected block is issued to an array control circuit. When an erase pass message is received, a judging step is performed to judge whether a setting condition of the selected block is satisfied. If the setting condition of the selected block is satisfied, the selected block is recorded as a good block. If the setting condition of the selected block is not satisfied, a selected block reverification process is performed. During the selected block reverification process, a data of the selected block is read and the selected block is recorded as the good block or a defective block according to a number of memory cells of the selected block in a non-erase state.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: September 3, 2019
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chun-Wei Kuo, Ding-Chiuan Huang, Shih-Jia Zeng
  • Patent number: 10347330
    Abstract: A reading control method for a solid state storage device includes following steps. While the solid state storage device is in an idle mode, a background monitoring operation is performed on the first block and the second block. Consequently, a first optimal read voltage set corresponding to the first block and a second optimal read voltage set corresponding to the second block are acquired. In reading operation, a default read voltage set is provided to the non-volatile memory to read a data of the first block. If a data of the first block is not successfully decoded, a read retry process is performed on the first block and the first optimal read voltage set is provided to the non-volatile memory to read the data of the first block.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: July 9, 2019
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu
  • Patent number: 10319428
    Abstract: A control method of a solid state storage device includes the following steps. Firstly, a block of a memory cell array is checked. Then, a judging step is performed to judge whether a data storage time period of the block exceeds a threshold period. If the data storage time period of the block exceeds the threshold period, the block is tagged or a data of the block is refreshed.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 11, 2019
    Assignee: LITE-ON TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Kuan-Chun Chen
  • Publication number: 20190164068
    Abstract: A method of building a decoding status prediction system is provided. Firstly, plural read records are collected during read cycles of a flash memory. Then, the plural read records are classified into read records with a first read result and read records with a second read result. Then, a first portion of the read records with the first read result are divided into K0 groups according to a clustering algorithm, and a second portion of the read records with the second read result are divided into K1 groups according to the clustering algorithm. Then, the read records of the K0 groups and the K1 groups are used to train prediction models. Consequently, K0×K1 prediction models are generated. Then, the prediction models are combined as a prediction database.
    Type: Application
    Filed: February 1, 2018
    Publication date: May 30, 2019
    Inventors: Yen-Chin LIAO, Ching-Hui Huang, Shih-Jia Zeng, Hsie-Chia Chang