Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.

Abstract: A read table management method for a solid state storage device includes the following steps. If the lowest computation value in a hot group is lower than the highest computation value in a cold group when a read table adjusting process is enabled, a first read voltage set corresponding to the lowest computation value in the hot group and a second read voltage set corresponding to the highest computation value in the cold group are swapped with each other. Consequently, the second read voltage set becomes to belong to the hot group, and the first read voltage set becomes to belong to the cold group.

Abstract: A solid state storage device is in communication with a host. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit is in communication with the host. The control circuit includes an error correction circuit and a prediction model storage circuit. A prediction model is stored in the prediction model storage circuit. The non-volatile memory includes a memory cell array. The memory cell array includes plural blocks. Each of the blocks includes a corresponding state parameter. The control circuit determines a selected block from the memory cell array. The control circuit judges whether to perform a specified operation on the selected block according to the state parameter of the selected block and the prediction model.

Abstract: A failure mode detection method is provided. A first default read voltage is changed to a first read retry voltage by a first increment, and a second default read voltage is changed to a second read retry voltage by a second increment. A memory cell array of a solid state storage device is successfully read according to the first and second read retry voltages. If an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, the memory cell array is in a data retention failure mode. If the absolute value of the first increment minus the absolute value of the second increment is smaller than the predetermined voltage value, the memory cell array is in a low temperature write high temperature read failure mode.

Abstract: An erased block reverification method for a solid state storage device is provided. Firstly, an erase command corresponding to a selected block is issued to an array control circuit. When an erase pass message is received, a judging step is performed to judge whether a setting condition of the selected block is satisfied. If the setting condition of the selected block is satisfied, the selected block is recorded as a good block. If the setting condition of the selected block is not satisfied, a selected block reverification process is performed. During the selected block reverification process, a data of the selected block is read and the selected block is recorded as the good block or a defective block according to a number of memory cells of the selected block in a non-erase state.

Abstract: A reading control method for a solid state storage device includes following steps. While the solid state storage device is in an idle mode, a background monitoring operation is performed on the first block and the second block. Consequently, a first optimal read voltage set corresponding to the first block and a second optimal read voltage set corresponding to the second block are acquired. In reading operation, a default read voltage set is provided to the non-volatile memory to read a data of the first block. If a data of the first block is not successfully decoded, a read retry process is performed on the first block and the first optimal read voltage set is provided to the non-volatile memory to read the data of the first block.

Abstract: A control method of a solid state storage device includes the following steps. Firstly, a block of a memory cell array is checked. Then, a judging step is performed to judge whether a data storage time period of the block exceeds a threshold period. If the data storage time period of the block exceeds the threshold period, the block is tagged or a data of the block is refreshed.

Abstract: A method of building a decoding status prediction system is provided. Firstly, plural read records are collected during read cycles of a flash memory. Then, the plural read records are classified into read records with a first read result and read records with a second read result. Then, a first portion of the read records with the first read result are divided into K0 groups according to a clustering algorithm, and a second portion of the read records with the second read result are divided into K1 groups according to the clustering algorithm. Then, the read records of the K0 groups and the K1 groups are used to train prediction models. Consequently, K0×K1 prediction models are generated. Then, the prediction models are combined as a prediction database.

Abstract: A control method of a solid state storage device includes the following steps. Firstly, a block of a memory cell array is checked. Then, a judging step is performed to judge whether a data storage time period of the block exceeds a threshold period. If the data storage time period of the block exceeds the threshold period, the block is tagged or a data of the block is refreshed.

Abstract: A solid state storage device includes a non-volatile memory and a controlling circuit. In a first read retry process, the controlling circuit judges whether an information corresponding to a first block of the non-volatile memory is recorded in the cache table. If the information is not recorded in the cache table, the controlling circuit sequentially provides plural predetermined retry read voltage sets to the non-volatile memory according to a sequence of the plural predetermined retry read voltage sets in the retry table and performs a read retry operation. If a read data of the first block is successfully decoded through the read retry operation according to a first predetermined retry read voltage set of the plural predetermined retry read voltage sets in the retry table, the controlling circuit records the first predetermined retry read voltage set into the cache table.

Abstract: A solid state storage device includes a non-volatile memory and a controlling circuit. In a first read retry process, the controlling circuit judges whether an information corresponding to a first block of the non-volatile memory is recorded in the cache table. If the information is not recorded in the cache table, the controlling circuit sequentially provides plural predetermined retry read voltage sets to the non-volatile memory according to a sequence of the plural predetermined retry read voltage sets in the retry table and performs a read retry operation. If a read data of the first block is successfully decoded through the read retry operation according to a first predetermined retry read voltage set of the plural predetermined retry read voltage sets in the retry table, the controlling circuit records the first predetermined retry read voltage set into the cache table.

Abstract: A solid state storage includes a non-volatile memory and a controlling circuit. The non-volatile memory includes a first block. The controlling circuit is connected with the non-volatile memory. The controlling circuit includes a function storage circuit. The function storage circuit stores plural prediction functions. According to plural state parameters corresponding to the first block and a first prediction function of the plural prediction functions, the controlling circuit predicts a read voltage shift of the first block.

Abstract: A solid state storage includes a non-volatile memory and a controlling circuit. The non-volatile memory includes a first block. The controlling circuit is connected with the non-volatile memory. The controlling circuit includes a function storage circuit. The function storage circuit stores plural prediction functions. According to plural state parameters corresponding to the first block and a first prediction function of the plural prediction functions, the controlling circuit predicts a read voltage shift of the first block.

Abstract: A power-off period estimating method for a solid state storage device is provided. A memory array of a non-volatile memory of the solid state storage device includes plural blocks. Firstly, a first quality parameter of a first block of the plural blocks is calculated before the solid state storage device is powered off. When the first block is corrected at a first time counting value, a first read voltage set of the first block is acquired and the first time counting value is recorded. Then, the first block is corrected after the solid state storage device is powered on, so that a second read voltage set of the first block is acquired. Then, a power-off period is calculated according to the first quality parameter, the first read voltage set, the second read voltage set and the first time counting value.

Abstract: A power-off period estimating method for a solid state storage device is provided. A memory array of a non-volatile memory of the solid state storage device includes plural blocks. Firstly, a first quality parameter of a first block of the plural blocks is calculated before the solid state storage device is powered off. When the first block is corrected at a first time counting value, a first read voltage set of the first block is acquired and the first time counting value is recorded. Then, the first block is corrected after the solid state storage device is powered on, so that a second read voltage set of the first block is acquired. Then, a power-off period is calculated according to the first quality parameter, the first read voltage set, the second read voltage set and the first time counting value.

Abstract: A reading control method for a solid state storage device includes following steps. While the solid state storage device is in an idle mode, a background monitoring operation is performed on the first block and the second block. Consequently, a first optimal read voltage set corresponding to the first block and a second optimal read voltage set corresponding to the second block are acquired. In reading operation, a default read voltage set is provided to the non-volatile memory to read a data of the first block. If a data of the first block is not successfully decoded, a read retry process is performed on the first block and the first optimal read voltage set is provided to the non-volatile memory to read the data of the first block.

Abstract: A reading control method for a solid state storage device includes following steps. If a hard decoding process fails, a first histogram parameter and a second histogram parameter are generated in the hard decoding process according to a first sensing voltage, a second sensing voltage and a third sensing voltage. Then, a voltage shift amount is obtained according to the first histogram parameter, the second histogram parameter and a voltage shift function. The first sensing voltage, the second sensing voltage and the third sensing voltage are updated according to the voltage shift amount. Then, a soft decoding process is performed. The updated first sensing voltage, the updated second sensing voltage and the updated third sensing voltage are provided to a non-volatile memory, so that the non-volatile memory generates a soft data.

Abstract: A method for determining a storing state of a flash memory is provided. The method includes the following steps. Firstly, plural first specific cell patterns are programmed into the flash memory. Then, plural second specific cell patterns are programmed into the flash memory. Then, a slicing voltage is adjusted to allow a distinguishable error percentage to be lower than a predetermined value. Afterwards, a first storing state and a second storing state of other cells of the flash memory are distinguished from each other according to the adjusted slicing voltage.

Abstract: A defective address information encoding method for a memory array is provided. A page of the memory array is divided into plural segments. Each segment contains 2m bits. The defective address information encoding method includes the following steps. Firstly, positions of N1 fail bits in a first segment of the plural segments are acquired. Then, an (N1+1)-bit first segment start code is generated. Then, N1 m-bit defective codes are generated. The N1 m-bit defective codes follow the first segment start code to indicate the positions of the N1 fail bits in the first segment, wherein N1 is zero or a positive integer, and m is a positive integer.

Abstract: A defective address information encoding method for a memory array is provided. A page of the memory array is divided into plural segments. Each segment contains 2m bits. The defective address information encoding method includes the following steps. Firstly, positions of N1 fail bits in a first segment of the plural segments are acquired. Then, an (N1+1)-bit first segment start code is generated. Then, N1 m-bit defective codes are generated. The N1 m-bit defective codes follow the first segment start code to indicate the positions of the N1 fail bits in the first segment, wherein N1 is zero or a positive integer, and m is a positive integer.