Patents by Inventor Shih-Kuang Chen
Shih-Kuang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096867Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
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Patent number: 10714528Abstract: A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.Type: GrantFiled: November 1, 2018Date of Patent: July 14, 2020Assignee: XINTEC INC.Inventors: Hsin Kuan, Shih-Kuang Chen, Chin-Ching Huang, Chia-Ming Cheng
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Publication number: 20190140012Abstract: A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.Type: ApplicationFiled: November 1, 2018Publication date: May 9, 2019Inventors: Hsin KUAN, Shih-Kuang CHEN, Chin-Ching HUANG, Chia-Ming CHENG
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Publication number: 20160380024Abstract: A method for fabricating an image sensor chip package begins at providing a wafer, which includes forming a plurality of image sensor components on a substrate, forming a plurality of spacers on the substrate for separating the image sensor components, and disposing a transparent plate on the spacers. The method further includes forming a plurality of stress notches on the transparent plate. After the stress notches are formed, the transparent plate is pressed and the substrate is cut at the second chambers. The transparent plate is broken along the stress notches.Type: ApplicationFiled: September 9, 2016Publication date: December 29, 2016Inventors: Chih-Hao CHEN, Bai-Yao LOU, Shih-Kuang CHEN
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Patent number: 9449897Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer disposed between the surface of the semiconductor substrate and the protection plate, wherein the protection plate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface.Type: GrantFiled: March 5, 2014Date of Patent: September 20, 2016Assignee: XINTEC INC.Inventors: Bai-Yao Lou, Shih-Kuang Chen, Sheng-Yuan Lee
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Patent number: 9023676Abstract: A wafer packaging method includes the following steps. A light transmissive carrier is provided. A hydrolytic temporary bonding layer is formed on the light transmissive carrier. A first surface of a light transmissive protection sheet is bonded to the hydrolytic temporary bonding layer, such that the hydrolytic temporary bonding layer is located between the light transmissive protection sheet and the light transmissive carrier. A second surface of the light transmissive protection sheet facing away from the first surface is bonded to a third surface of a wafer. The light transmissive carrier, the hydrolytic temporary bonding layer, the light transmissive protection sheet, and the wafer are immersed in a high temperature liquid, such that adhesion force of the hydrolytic temporary bonding layer is eliminated. The light transmissive protection sheet and the wafer are obtained from the high temperature liquid.Type: GrantFiled: January 28, 2014Date of Patent: May 5, 2015Assignee: Xintec Inc.Inventors: Chih-Hao Chen, Bai-Yao Lou, Shih-Kuang Chen
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Publication number: 20140252642Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer disposed between the surface of the semiconductor substrate and the protection plate, wherein the protection plate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface.Type: ApplicationFiled: March 5, 2014Publication date: September 11, 2014Applicant: XINTEC INC.Inventors: Bai-Yao LOU, Shih-Kuang CHEN, Sheng-Yuan LEE
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Publication number: 20140213010Abstract: A wafer packaging method includes the following steps. A light transmissive carrier is provided. A hydrolytic temporary bonding layer is formed on the light transmissive carrier. A first surface of a light transmissive protection sheet is bonded to the hydrolytic temporary bonding layer, such that the hydrolytic temporary bonding layer is located between the light transmissive protection sheet and the light transmissive carrier. A second surface of the light transmissive protection sheet facing away from the first surface is bonded to a third surface of a wafer. The light transmissive carrier, the hydrolytic temporary bonding layer, the light transmissive protection sheet, and the wafer are immersed in a high temperature liquid, such that adhesion force of the hydrolytic temporary bonding layer is eliminated. The light transmissive protection sheet and the wafer are obtained from the high temperature liquid.Type: ApplicationFiled: January 28, 2014Publication date: July 31, 2014Applicant: Xintec Inc.Inventors: Chih-Hao CHEN, Bai-Yao LOU, Shih-Kuang CHEN
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Publication number: 20140191350Abstract: An image sensor chip package is disclosed, which includes a substrate, an image sensor component formed on the substrate, a spacer formed on the substrate and surrounding the image sensor component, and a transparent plate. A stress notch is formed on a side of the transparent plate, and a breaking surface is extended from the stress notch. A method for fabricating the image sensor chip package is also disclosed.Type: ApplicationFiled: January 8, 2014Publication date: July 10, 2014Applicant: XINTEC INC.Inventors: Chih-Hao CHEN, Bai-Yao LOU, Shih-Kuang CHEN
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Patent number: 8035213Abstract: A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a package portion and a plurality of external conductors. The package portion includes a distribution layer, a chip, a plurality internal conductors and a sealant. The distribution layer has a first surface and a second surface, and the chip is disposed on the first surface. Each internal conductor has a first terminal and a second terminal. The first terminal is disposed on the first surface. The sealant is disposed on the first surface for covering the chip and partly encapsulating the internal conductors, so that the first terminal and the second terminal of each internal conductor are exposed from the sealant. The external conductors disposed on the second surface of the distribution layer of the package portion are electrically connected to the internal conductors.Type: GrantFiled: October 1, 2008Date of Patent: October 11, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chang-Chi Lee, Shih-Kuang Chen, Yuan-Ting Chang
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Patent number: 7651937Abstract: A bumping process and a structure thereof are provided. The bumping process includes the following steps. Firstly, a wafer having a number of pads is provided. Next, a UBM layer is formed on the pad. Then, a conductive first photo-resist layer is coated on the wafer to cover the UBM layer. Next, a second photo-resist layer is coated on the first photo-resist layer. Then, at least a portion of the second photo-resist layer is removed to form an opening above the UBM layer. The first photo-resist layer maintains electric connection with the UBM layer. Next, a solder layer is formed in the opening by electroplating process. Then, the first photo-resist layer and the second photo-resist layer are removed expect the portion of the first photo-resist layer under the solder layer.Type: GrantFiled: August 11, 2006Date of Patent: January 26, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chueh-An Hsieh, Li-Cheng Tai, Shyh-Ing Wu, Shih-Kuang Chen
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Publication number: 20090102066Abstract: A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a package portion and a plurality of external conductors. The package portion includes a distribution layer, a chip, a plurality internal conductors and a sealant. The distribution layer has a first surface and a second surface, and the chip is disposed on the first surface. Each internal conductor has a first terminal and a second terminal. The first terminal is disposed on the first surface. The sealant is disposed on the first surface for covering the chip and partly encapsulating the internal conductors, so that the first terminal and the second terminal of each internal conductor are exposed from the sealant. The external conductors disposed on the second surface of the distribution layer of the package portion are electrically connected to the internal conductors.Type: ApplicationFiled: October 1, 2008Publication date: April 23, 2009Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang-Chi Lee, Shih-Kuang Chen, Yuan-Ting Chang
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Patent number: 7518241Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.Type: GrantFiled: August 31, 2006Date of Patent: April 14, 2009Assignee: Advanced Semiconductor Engineering Inc.Inventors: Li-Cheng Tai, Jui-I Yu, Jiunn Chen, Chueh-An Hsieh, Shyh-Ing Wu, Shih-Kuang Chen, Tsung-Chieh Ho, Tsung-Hua Wu
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Publication number: 20070108612Abstract: A chip structure and a manufacturing method of the same. The chip structure includes a base, a pad, a first passivation layer, a second passivation layer and a bump. The pad is formed on the base. The first passivation layer is formed on the base exposing the pad. The second passivation layer formed on the first passivation layer has a passivation layer opening which is positioned above the pad. The bump is formed on the pad, and a part of the bump is disposed inside the passivation layer opening. The width at the bottom of the passivation layer opening is larger than the width at the top of the passivation layer opening, such that the bump is firmly fixed by the second protection layer.Type: ApplicationFiled: August 29, 2006Publication date: May 17, 2007Inventors: Chueh-An Hsieh, Li-Cheng Tai, Shyh-Ing Wu, Shih-Kuang Chen
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Publication number: 20070045848Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.Type: ApplicationFiled: August 31, 2006Publication date: March 1, 2007Inventors: Li-Cheng Tai, Jui-I Yu, Jiunn Chen, Chueh-An Hsieh, Shyh-Ing Wu, Shih-Kuang Chen, Tsung-Chieh Ho, Tsung-Hua Wu
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Publication number: 20070049001Abstract: A bumping process and a structure thereof are provided. The bumping process includes the following steps. Firstly, a wafer having a number of pads is provided. Next, a UBM layer is formed on the pad. Then, a conductive first photo-resist layer is coated on the wafer to cover the UBM layer. Next, a second photo-resist layer is coated on the first photo-resist layer. Then, at least a portion of the second photo-resist layer is removed to form an opening above the UBM layer. The first photo-resist layer maintains electric connection with the UBM layer. Next, a solder layer is formed in the opening by electroplating process. Then, the first photo-resist layer and the second photo-resist layer are removed expect the portion of the first photo-resist layer under the solder layer.Type: ApplicationFiled: August 11, 2006Publication date: March 1, 2007Inventors: Chueh-An Hsieh, Li-Cheng Tai, Shyh-Ing Wu, Shih-Kuang Chen
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Patent number: 6737353Abstract: A semiconductor device having a bump electrode comprising a substrate having a dielectric layer formed thereon, an aluminum contact pad on the substrate wherein at least a portion of the aluminum contact pad is exposed through the dielectric layer on the substrate. The aluminum contact pad is provided with an under bump metallurgy including a aluminum layer formed on the exposed portion of the aluminum contact pad, a nickel-vanadium layer formed on the aluminum layer and a titanium layer formed on the nickel-vanadium layer. A gold bump formed on the titanium layer acts as the bump electrode.Type: GrantFiled: June 19, 2001Date of Patent: May 18, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jen Kuang Fang, Ching Hua Chiang, Shih Kuang Chen, Chau Fu Weng
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Patent number: 6716736Abstract: In a method for manufacturing an under-bump metallurgy (UBM) layer, a plate having a plurality of openings is prepared. Then, the plate is placed on the wafer. Finally, the material of the under-bump metallurgy layer is sputtered on the wafer using the plate as a sputter mask so as to quickly form the under-bump metallurgy layer.Type: GrantFiled: January 14, 2002Date of Patent: April 6, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Shih-Kuang Chen, Chih-Hsiang Hsu
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Patent number: 6692581Abstract: A solder paste for fabricating bumps includes a flux and metallic alloy powder. The metallic alloy powder includes a plurality of low eutectic metallic alloy granules, and the size of these metallic alloy granules is 20-60 &mgr;m and the average size of the metallic granules is 35 &mgr;m to 45 &mgr;m.Type: GrantFiled: February 20, 2003Date of Patent: February 17, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Ching-Fu Horng, Shih-Kuang Chen, Shyh-Ing Wu, Chun-Hung Lin, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Patent number: D1020435Type: GrantFiled: November 8, 2021Date of Patent: April 2, 2024Assignee: BROGENT TECHNOLOGIES INC.Inventors: Shih-Kuang Chiu, Chia-Wei Yeh, Juei-Tsung Chen