Abstract: An integrated circuit is fabricated using a semiconductor fabrication process. One or more uncontrollable random physical processes in the semiconductor fabrication process can cause small differences between the integrated circuit and other similarly designed integrated circuit. These small differences can cause transistors of the integrated circuit to have different threshold voltages. The integrated circuit can use these different threshold voltages to quantify its physical uniqueness to differentiate itself from other integrated circuits similarly designed and fabricated by the semiconductor fabrication process.

Abstract: A memory device, includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array, wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span a first equal number of rows and columns and the second plurality of diagonal bit cells also span a second equal number of rows and columns.

Abstract: A memory device is provided. The memory device includes a memory array including a plurality of sections, and an inter-hamming difference analyzer. Each of the sections has an individual location in the memory array. The inter-hamming difference analyzer is configured to obtain a plurality of inter-hamming differences according to the number of unlike bits between content of each section of the plurality of sections corresponding to a first operating condition and content of another section of the plurality of sections corresponding to a second operating condition.

Abstract: Methods and apparatus for protecting a physical unclonable function (PUF) generator are disclosed. In one example, a PUF generator is disclosed. The PUF generator includes a PUF cell array, a PUF control circuit and a reset circuit. The PUF cell array comprises a plurality of bit cells. Each of the plurality of bit cells is configurable into at least two different stable states. The PUF control circuit is coupled to the PUF cell array and is configured to access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a PUF signature based on the determined stable states of the plurality of bit cells. The reset circuit is coupled to the PUF cell array and is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the PUF cell array.

Abstract: A memory circuit includes a first memory cell, a second memory cell, a pre-charge circuit and a sense amplifier. The pre-charge circuit is coupled to a first bit line and a second bit line. The pre-charge circuit is configured to charge the first bit line and the second bit line to a pre-charge voltage level responsive to a first signal. The sense amplifier is coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line. The sense amplifier is responsive to a second signal and a third signal. The second signal and the third signal being different from the first signal.

Abstract: A method includes retrieving a registered response obtained in a registration process, the registered response being a physically unclonable function (PUF)-based response associated with a device; retrieving a registered helper data obtained in the registration process, the registered helper data corresponding to the registered response; generating a cipher text by encrypting a message with the registered response; and sending to the device over a public channel the cipher text with the registered helper data.

Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a testing method for physical unclonable function (PUF) generator includes: verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array; and determining whether the PUF generator is a qualified PUF generator based on whether one or more predefine quality criteria is satisfied.

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

Abstract: A circuit includes a first cell in a first row of a memory array, a second cell in a second row of the memory array, and a data line perpendicular to the first row and the second row, intersecting each of the first cell and the second cell, and electrically coupled with each of the first cell and the second cell. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a read operation on the first row.

Abstract: A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.

Abstract: A circuit includes a memory configured to store a data unit and parity bits, the parity bits being based on a write address associated with the stored data unit. An address port is configured to receive a read address for the stored data unit. A decoding circuit is configured to generate a decoded write address from the read address and the parity bits, and an error detecting circuit is configured to determine if an address error exists based on a comparison of the decoded write address to the read address.

Abstract: Methods and apparatus for protecting a physical unclonable function (PUF) generator are disclosed. In one example, a PUF generator is disclosed. The PUF generator includes a PUF cell array, a PUF control circuit and a reset circuit. The PUF cell array comprises a plurality of bit cells. Each of the plurality of bit cells is configurable into at least two different stable states. The PUF control circuit is coupled to the PUF cell array and is configured to access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a PUF signature based on the determined stable states of the plurality of bit cells. The reset circuit is coupled to the PUF cell array and is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the PUF cell array.

Abstract: A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.

Abstract: A memory device, includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array, wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span a first equal number of rows and columns and the second plurality of diagonal bit cells also span a second equal number of rows and columns.

Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates.

Abstract: Methods and systems for generating a signature for a device include pre-charging a plurality of conductors to a first voltage level. A voltage leakage for each of the conductors is determined, and a device signature is generating based on the determined leakage.

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: A physically unclonable function (PUF) cell array includes a first PUF cell arranged in a first column in a first direction and a second PUF cell arranged in a second column in the first direction. The first PUF cell includes a first set of conductive structures extending in the first and a second direction. The second PUF cell includes a second set of conductive structures extending in the first and the second direction. The first PUF cell includes a first conductive structure and a second conductive structure extending in the second direction. The second PUF cell includes a third conductive structure and a fourth conductive structure extending in the second direction. The first and third conductive structure or the second and fourth conductive structure are symmetric to each other with respect to a central line of at least the first or second PUF cell extending in the second direction.

Abstract: A device is disclosed for testing a memory, in which the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response in responses of the first memory circuit, and the first memory circuit is configured to store a second response of responses of the second memory circuit. The device includes a comparing circuit and a maximum hamming distance generating circuit. The comparing circuit is configured to compare the first response with the responses of the first memory circuit, and configured to compare the second response with the responses of the second memory circuit, to generate comparing results. The maximum hamming distance generating circuit is configured to generate a maximum hamming distance according to the comparing results.

Abstract: A physically unclonable function (PUF) device is provided. The PUF device includes: a plurality of PUF cells configured to generate an output. Each of the plurality of cells includes a sense amplifier, a load circuit. The sense amplifier includes a first circuit and a second circuit configured to generate a bit line and a complementary bit line. The sense amplifier having a first circuit and a second circuit configured to generate a bit line and a complementary bit line. The first circuit generates an output at a first output node and the second circuit generates an output at the second output node. The load circuit having a first transistor and a second transistor configured to generate a bias to the sense amplifier to obtain a mask bit at a first output node and a second output node. The control terminal of the first transistor is controlled by a first selection bit, and a control terminal of the second transistor is controlled by a second selection bit.