Abstract: A memory device, includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array, wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span a first equal number of rows and columns and the second plurality of diagonal bit cells also span a second equal number of rows and columns.

Abstract: An electronic device for checking a randomness of an identification key device, a random key checker circuit for an electronic device and a method of checking randomness for an electronic device. An electronic device for checking a randomness of an identification key device includes an identification key generator, configured to generate an identification key. A random key checker circuit, configured to receive the identification key from the identification key generator, calculates a randomness value of the identification key according to the identification key for checking a randomness of the identification key and generates an output of the identification key with high randomness.

Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a G matrix; transforming the G matrix into a systematic form, the transformed G matrix composed of a P matrix and a H matrix; sorting rows of the P matrix according to row weights; determining the number of rows in the P matrix to be truncated in view of a correcting strength and the number of data bits; generating a truncated P matrix by truncating the sorted rows of the P matrix that have a first row weights and keeping the sorted rows of the P matrix that have a second row weights; and forming the error correction circuit according to the truncated P matrix to correct the error of the codeword; wherein the first row weights are greater than the second row weights.

Abstract: A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Abstract: A memory array includes a first memory cell and a second memory cell. Each of the first and the second memory cells includes a data storage element having a first terminal and a second terminal, a first access transistor coupled to the first terminal of the data storage element, and a second access transistor coupled to the second terminal of the data storage element. The memory array also includes a first word line and a second word line coupled to the first access transistor and the second access transistor, respectively, of the first memory cell, wherein the first word line and the second word line are operated independently during a read operation and activated at the same time during a write operation.

Abstract: A circuit includes a first cell in a first row of a memory array, a second cell in a second row of the memory array, and a data line perpendicular to the first row and the second row, intersecting each of the first cell and the second cell, and electrically coupled with each of the first cell and the second cell. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a read operation on the first row.

Abstract: An integrated circuit (IC) is provided. The IC includes a cache memory divided into a plurality of groups, and an address decoder. Each of the groups includes a plurality of sets, and one of the groups is assigned as a first group and the remaining groups are assigned as a plurality of second groups. The first group and the second groups are assigned in rotation for a plurality of time periods, and each of the groups is assigned in a corresponding single one of the time periods. The address decoder is configured to provide a physical address according to an access address of the cache memory. The sets of the first group that is assigned in a first time period are not overlapping with the sets of other first groups that are assigned in the time periods other than the first time period.

Abstract: Disclosed is a device and method to secure software update information for authorized entities. In one embodiment, a device for receiving secured software update information from a server, the device includes: a physical uncolonable function (PUF) information generator, comprising a PUF cell array, configured to generate PUF information, wherein the PUF information comprises at least one PUF response output, wherein the at least one PUF response output is used to encrypt the software update information on the server so as to generate encrypted software update information; a first encrypter, configured to encrypt the PUF information from the PUF information generator using one of at least one public key from the server so as to generate encrypted PUF information; and a second encrypter, configured to decrypt the encrypted software update information using one of the at least one PUF response output so as to obtain the software update information.

Abstract: A method for utilizing a plurality of physical unclonable function (PUF) cells to generate a signature key with a desired bit length is provided. The method includes setting a state of each of the plurality of PUF cells to a uniform level; obtaining an order of change in the state of at least a portion of the plurality of PUF cells; and generating the signature key at least based on the order.

Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.

Abstract: A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.

Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator, includes: a PUF cell array comprising a plurality of bit cells configured in at least one column and at least one row, wherein the plurality of bit cells each provides two voltage transient behaviors on two corresponding bit lines of the at least one column; and at least two load control circuits coupled to the two bit lines of the at least one corresponding column, wherein the at least two load control circuits are each configured to provide at least one discharge pathway to at least one of the two corresponding bit lines, wherein the at least one discharge pathway is configured to change at least one of the two voltage transient behaviors so as to determine stability of each of the plurality of bit cells of the PUF cell array.

Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.

Abstract: A physically unclonable function (PUF) device and a method for maximizing existing process variation for a physically unclonable device are provided. The method of maximizing process variation of the PUF device includes: modeling a physically unclonable function (PUF) device, comprising a plurality of PUF cells, selecting the size of transistors in the PUF device to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells, varying the material of the PUF device, and driving the PUF device with a predetermined voltage. The physically unclonable device includes: a plurality of PUF cells, configured to generate an output. Each of the plurality of PUF cells includes a harvester circuit, configured to generate a bit line and a complementary bit line.

Abstract: Disclosed is a device and method to secure PUF information for authorized entities. In one embodiment, a device for securing physically unclonable function (PUF) information includes: a PUF information generator, comprising a PUF cell array and a helper data generator, configured to generate the PUF information, wherein the PUF information comprises a PUF response and helper data; and a PUF information encrypter, comprising a memory unit and a first crypto-system, configured to store at least one public key and encrypt the PUF information from the PUF information generator using one of the at least one public key.

Abstract: A memory cell array includes a first memory cell, a word line and a first bit line. The first memory cell is arranged in a first row in a first direction. The word line extends in the first direction and is coupled to the first memory cell. The first bit line extends in a second direction different from the first direction, and is coupled to the first memory cell. The first memory cell corresponds to a five transistor (5T) memory cell. The first memory cell includes a first active region having a first length in the second direction, and a second active region having a second length in the second direction and being different from the first length. The first active region and the second active region extend in the second direction, are located on a first level and are separated from each other in the first direction.

Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates.

Abstract: A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.

Abstract: Disclosed is a physical unclonable function generator circuit and method.