Abstract: Provided are a memory device and a method of forming the same. The memory device includes a substrate, a multi-layer stack, a plurality of memory cells, and a plurality of conductive contacts. The substrate includes an array region and a staircase region. The multi-layer stack is disposed on the substrate in the array region, wherein the multi-layer stack has an end portion extending on the staircase region to be shaped into a staircase structure. The plurality of memory cells are respectively disposed on sidewalls of the multi-layer stack in the array region, and arranged at least along a stacking direction of the multi-layer stack. The plurality of conductive contacts are respectively on the staircase structure. At least two conductive contacts are electrically connected to each other.

Abstract: An integrated circuit is fabricated using a semiconductor fabrication process. One or more uncontrollable random physical processes in the semiconductor fabrication process can cause small differences between the integrated circuit and other similarly designed integrated circuit. These small differences can cause transistors of the integrated circuit to have different threshold voltages. The integrated circuit can use these different threshold voltages to quantify its physical uniqueness to differentiate itself from other integrated circuits similarly designed and fabricated by the semiconductor fabrication process.

Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.

Abstract: A circuit includes: a single-port memory interface which includes a sole address port configured to receive a read/write (RW) address, and a multi-port memory which has multiple address ports coupled to the sole address port of the single-port memory interface, and which is configured to store a data unit and parity bits, some of the parity bits being based on the corresponding RW address; a first decoding circuit configured to generate a decoded write address from the RW address and the parity bits; and an error detecting circuit configured to determine if an address error exists based on a comparison of the decoded write address to the read address.

Abstract: A client device is fabricated using a semiconductor fabrication process. One or more uncontrollable random physical processes in the semiconductor fabrication process can cause small differences between the client device and other client devices. When the client device is presented with a challenge from a server device, the client device generates a random response that depends on its physical properties. The server device stores this random response as a part of a virtual PUF circuitry storage device having other random responses from the other client devices. The server device uses the random response of the client device stored in the virtual PUF circuitry storage device for one or more encryption algorithms to encrypt information to be provided to the client device.

Abstract: A memory device is described, including a command decoder configured to receive a copy command to copy data stored in a first memory location to a second memory location without transmitting the data to an external controller, a memory array electrically connected to the command decoder and including a plurality of memory locations including the first memory location and the second memory location, a data line electrically connected to the memory array and configured to receive, from the first memory location, the data to be transmitted to the second memory location through the same data line, and an output buffer configured to store the data received from the first memory location through the data line to be written into the second memory location without transmitting the data to the external controller.

Abstract: A memory device is provided. The memory device includes a cell array having a plurality of cells, each of the plurality of cells operative to store a bit value. The memory device further includes a reset circuit connected to the cell array. The reset circuit is operative to reset, in parallel, the bit value stored in each of the plurality of cells to a predetermined bit value.

Abstract: An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.

Abstract: A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Abstract: A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive segment, a conductive layer, a first contact element and a second contact element. The semiconductor substrate includes an active region. The conductive segment is formed on the semiconductor substrate, and extends across the active region. The conductive layer is formed over the semiconductor substrate and the conductive segment. The first contact element, formed between the conductive segment and a first conductive portion of the conductive layer, is arranged to electrically connect the conductive segment to the first conductive portion. The second contact element is formed between the conductive segment and a second conductive portion of the conductive layer. The first contact element and the second contact element are formed on the conductive segment and spaced apart from each other. The second contact element is arranged to electrically isolate the conductive segment from the second conductive portion.

Abstract: Disclosed herein are related to an age detector for determining an age of a memory block, and a method of operation of the age detector. In one configuration, a memory system includes a memory block and an age detector coupled to the memory block. In one aspect, the memory block generates a first set of data in response to a first power on, and generates a second set of data in response to a second power on. In one configuration, the age detector includes a storage block to store the first set of data from the memory block, and inconsistency detector to compare the first set of data and the second set of data. In one configuration, the age detector includes a controller to determine an age of the memory block, based on the comparison.

Abstract: A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.

Abstract: An integrated circuit includes an error correction code (ECC) encoder configured to generate a first set of check bits in response to a first set of data, a first set of inverters coupled to the ECC encoder and being configured to generate a second set of check bits in response to the first set of check bits, and a first memory cell array. The second set of check bits is inverted from the first set of check bits. The first memory cell array includes a first portion of memory cells configured to store the first set of data, and a second portion of memory cells coupled to the first set of inverters, and configured to store the second set of check bits.

Abstract: An electronic device for checking a randomness of an identification key device, a random key checker circuit for an electronic device and a method of checking randomness for an electronic device. An electronic device for checking a randomness of an identification key device includes an identification key generator, configured to generate an identification key. A random key checker circuit, configured to receive the identification key from the identification key generator, calculates a randomness value of the identification key according to the identification key for checking a randomness of the identification key and generates an output of the identification key with high randomness.

Abstract: A system for processing a data array, such as transposing a matrix, includes a two-dimensional array of memory cells, such as FeFETs, each having an input end, an output end and a control end. The system also includes an input interface is adapted to supply signals indicative of a subset of the data array, such as a row of a matrix, and output control signals to the input ends of a selected column of the memory cells. The system further includes an output interface adapted to receive the data stored in the memory array from the output ends of a selected row of the memory cells. A method of processing a data array, such as transposing a matrix, include writing subsets of the data array to the memory array column-by-column, and reading from the memory cells, row-by-row.

Abstract: An integrated circuit layout is provided. The integrated circuit layout includes: a first active region having a first plurality of field effect transistors (FETs); and an interconnect contacting sources and drains of the first plurality of FETs in the first active region through a first set of contact structures. At least one of the first set of contact structures is electrically non-conductive.

Abstract: A method for utilizing a plurality of physical unclonable function (PUF) cells to generate a signature key with a desired bit length is provided. The method includes setting a state of each of the plurality of PUF cells to a uniform level; obtaining an order of change in the state of at least a portion of the plurality of PUF cells; and generating the signature key at least based on the order.

Abstract: Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.

Abstract: A memory circuit includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier is coupled to the first memory cell by a first bit line, and coupled to the second memory cell by a second bit line. The sense amplifier includes a header switch, a footer switch, a first cross-coupled inverter and a second cross-coupled inverter. The header switch has a first size, and is coupled to a first node and a first supply voltage. The footer switch has a second size, and is coupled to a second node and a second supply voltage. The first size is greater than the second size. The first size includes a first number of fins or a first channel width. The second size includes a second number of fins or a second channel width.