Abstract: A slim vapor chamber includes a first plate, a second plate and a capillary structure. The periphery of the second plate is connected with that of the first plate to form a chamber. The capillary structure is disposed in the chamber. At least one of a side of the first plate facing the second plate and a side of the second plate facing the first plate is formed with a plurality of supporting structures, which include a plurality of supporting pillars and a plurality of supporting plates, by an etching process.

Abstract: A heat pipe is disclosed in the present invention. The heat pipe includes a first pipe and at least a second pipe. The first pipe is formed with an enclosed space. The second pipe is disposed in the enclosed space. There is no wick structure disposed between the first pipe and the second pipe.

Abstract: A heat pipe is divided into an evaporation section, an insulation section and a condensation section. The insulation section includes a pipe section and a liquid delivery structure. The pipe section has a top wall and a bottom wall. The liquid delivery structure is a solid structure and in contact with the top and bottom walls of the pipe section. The liquid delivery structure and the top and bottom walls of the pipe section form a vapor channel. The liquid delivery structure is divided into a center portion and an outer layer, and the center portion has a porosity greater than the porosity of the outer layer. The outer layer is coupled to the center portion, and the center portion and the vapor channel are spaced from one another, so as to achieve the liquid and vapor isolation and improve the heat conducting effect of the heat pipe.

Abstract: A heat pipe comprises a pipe and at least a wick structure. The pipe includes a hollow chamber. The wick structure is disposed in the hollow chamber and extended along an axial direction of the pipe. A section of the wick structure along the axial direction is not a uniform section between two ends of the pipe.

Abstract: A heat pipe comprises a first pipe and at least a second pipe. The first pipe includes an evaporator, a heat insulator and a condenser communicating with each other to define a hollow chamber. Two ends of first pipe along an axial direction of the heat pipe are sealed. The second pipe is disposed in the hollow chamber and includes an accommodating space and a first capillary structure disposed in one end of the accommodating space closer to the evaporator. The hollow chamber of the first pipe is mainly a channel for vapor, the second pipe is mainly a channel for working fluid, the vapor is driven by the vapor pressure difference to move in the first pipe and from the evaporator to the condenser, and the working fluid is driven by the vapor pressure difference to flow in the second pipe and from the condenser to the evaporator.

Abstract: A PSMA-specific imaging agent comprising a compound according to formula I: are described, wherein S1 is an organic spacer group having from 5 to 30 carbons, A is an amino acid forming a portion of a negatively charged peptide oligomer, n is from 3 to 6, S2 is an organic spacer group having from 5 to 15 carbons, and I is an imaging group, and pharmaceutically acceptable salts thereof. The PSMA-specific imaging agents can be used to image PSMA within a tissue region to guide the treatment of diseases such as prostate cancer.

Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage.

Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage.

Abstract: A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set.

Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

Abstract: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

Abstract: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

Abstract: An antenna device includes two antenna members each having a support member disposed on a transmission facility, and two helical antenna elements disposed on the support members and arranged in different directions or opposite to each other and having polar directions preferably arranged perpendicular to each other for facilitating a throughput or signal transmitting effect and for increasing the isolation. The helical antenna elements each may include a terminal electrically coupled to a cable, and each may include two or more helical conductors and one or more non-conducting spaces disposed between the helical conductors.

Abstract: A method of treating organic compounds in groundwater utilizes permeable catalytic barriers to carry out heterogeneous catalytic oxidation to degrade organic compounds. The permeable catalytic barriers are made of highly permeable catalytic materials, used to contact with the polluted groundwater mixed with oxidant to carry out heterogeneous catalytic oxidation to degrade organic compounds. Ditches are properly excavated to be filled with catalytic materials so as to form the permeable catalytic barriers. And, groundwater monitoring wells and oxidant injection wells are also built at proper locations, so that proper amount of oxidant can be determined and re-treatment can be promptly operated if necessary.