Patents by Inventor Shih-Ming Chang
Shih-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8828885Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed.Type: GrantFiled: January 4, 2013Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh, Ru-Gun Liu
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Patent number: 8806392Abstract: A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.Type: GrantFiled: December 3, 2012Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Tzu-Chin Lin, Jen-Chieh Lo, Yu-Po Tang, Tsong-Hua Ou
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Publication number: 20140220493Abstract: A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate.Type: ApplicationFiled: February 1, 2013Publication date: August 7, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu
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Patent number: 8779592Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.Type: GrantFiled: May 1, 2012Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Po Tang, Shih-Ming Chang, Ken-Hsien Hsieh, Ru-Gun Liu
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Publication number: 20140193981Abstract: One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed.Type: ApplicationFiled: January 4, 2013Publication date: July 10, 2014Applicant: Taiwan Semiconductor Mnufacturing Company LimitedInventors: Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai, Ken-Hsien Hsieh, Ru-Gun Liu
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Patent number: 8758963Abstract: A hologram reticle and method of patterning a target. A layout pattern for an image to be transferred to a target is converted into a holographic representation of the image. A hologram reticle is manufactured that includes the holographic representation. The hologram reticle is then used to pattern the target. Three-dimensional patterns may be formed in a photoresist layer of the target in a single patterning step. These three-dimensional patterns may be filled to form three-dimensional structures or else used in a multi-surface imaging composition. The holographic representation of the image may also be transferred to a top photoresist layer of a top surface imaging (TSI) semiconductor device, either directly or using the hologram reticle. The top photoresist layer may then be used to pattern an underlying photoresist layer with the image. The lower photoresist layer is used to pattern a material layer of the device.Type: GrantFiled: July 20, 2012Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Chung-Hsing Chang, Wen-Chuan Wang, Chi-Lun Lu, Sheng-Chi Chin, Chin-Hsiang Lin, Chun-Kuang Chen
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Publication number: 20140157212Abstract: A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.Type: ApplicationFiled: December 3, 2012Publication date: June 5, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Tzu-Chin Lin, Jen-Chieh Lo, Yu-Po Tang, Tsong-Hua Ou
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Patent number: 8716841Abstract: A photolithography mask and method includes receiving a layout of an integrated circuit including main pattern elements, inserting an array of dummy pattern elements between and around the main pattern elements, analyzing a diffraction spectrum of at least one of the main pattern elements and the array of dummy pattern elements, and varying one or more of a first pitch between corresponding features of dummy pattern elements adjacent to each other in a first direction and a second pitch between corresponding features of dummy pattern elements adjacent to each other in a second direction based on the analyzed diffraction spectrum to form a modified array of dummy pattern elements. The diffraction spectrum of the modified array of dummy pattern elements and the main pattern elements is more diffuse than a diffraction spectrum of a corresponding array of dummy pattern elements in which neither the first nor second pitch are varied and the main pattern elements.Type: GrantFiled: March 14, 2013Date of Patent: May 6, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Shuo-Yen Chou
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Patent number: 8707437Abstract: Keyloggers are detected in a computer. A test string is generated in the computer. Keyboard input is simulated using the test string. The test string may be input to a hidden browser connected to a sensitive site or a hidden application program, for example. Files modified during the input procedure are detected. Processes running in memory and modified files are scanned for presence of the test string to detect keyloggers.Type: GrantFiled: April 18, 2011Date of Patent: April 22, 2014Assignee: Trend Micro IncorporatedInventors: Shih Ming-Chang, Webber Han, Peggy Wu
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Publication number: 20130328778Abstract: A method of simulating the touch screen operation by means of a mouse is provided and particularly makes the mouse work in a computer operating system with a screen touch function. The mouse comprises at least one simulation touch trigger button and one touch signal converter unit. Press the simulation touch trigger button, and the mouse will work in the touch mode. The touch signal converter unit intercepts a pressed button signal of the mouse and converts it into a screen touch signal for executing single-finger or multi-finger slide and touch functions. The mouse is further provided with a fixed-point button, and when the fixed-point button is pressed, where the mouse is corresponding to the screen, a finger press is simulated. The pressed position is fixed and does not move, and another button of the mouse is pressed to operate for executing the screen zoom-in, zoom-out, and rotation.Type: ApplicationFiled: August 6, 2012Publication date: December 12, 2013Inventors: Kuan-Ting CHEN, Shih-Ming Chang, Li-Chieh Wang
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Publication number: 20130292836Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.Type: ApplicationFiled: May 1, 2012Publication date: November 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Po Tang, Shih-Ming Chang, Ken-Hsien Hsieh, Ru-Gun Liu
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Publication number: 20130285246Abstract: A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou
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Publication number: 20130270704Abstract: A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.Type: ApplicationFiled: April 11, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou
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Patent number: 8413606Abstract: A feed carrier receptacle for use in a rotary feed dispensing mechanism, which includes a box, a feed loading opening, and separation partitions. The feed loading opening is formed in the box. The separation partitions are arranged inside the box and every adjacent separation partitions and an inside surface of the box form a feed compartment, which communicates the feed loading opening and is provided with a feed discharge opening and a brush adjacent to the feed discharge opening When put into rotation, the feed loaded in the receptacle is generally rotated in unison therewith to move toward the feed discharge openings and is subject to a frictional force as contacting the brush so that the feed, when passing through the brush, is caused to rotate by itself and thus may fly over a long distance. This increases the distribution range of feed.Type: GrantFiled: August 23, 2011Date of Patent: April 9, 2013Assignee: Cixi Haosheng Electronics & Hardware Co., Ltd.Inventors: Shih-Ming Chang, Jin-Jun Cao
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Publication number: 20130047927Abstract: Disclosed is a feed carrier receptacle for use in a rotary feed dispensing mechanism, which includes a box, a feed loading opening, and separation partitions. The feed loading opening is formed in the box. The separation partitions are arranged inside the box and every adjacent separation partitions and an inside surface of the box form a feed compartment, which communicates the feed loading opening and is provided with a feed discharge opening and a brush adjacent to the feed discharge opening. When put into rotation, the feed loaded in the receptacle is generally rotated in unison therewith to move toward the feed discharge openings and is subject to a frictional force as contacting the brush so that the feed, when passing through the brush, is caused to rotate by itself and thus may fly over a long distance. This increases the distribution range of feed.Type: ApplicationFiled: August 23, 2011Publication date: February 28, 2013Inventors: SHIH-MING CHANG, Jin-Jun Cao
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Patent number: 8378319Abstract: A direct-write system is provided which includes a stage for holding a substrate, a processing module for processing pattern data and generating instructions associated with the pattern data, and an exposure module that includes beams that are focused onto the substrate and a beam controller that controls the beams in accordance with the instructions. The processing module includes vertex pair processors each having bit inverters. Each vertex pair processor is operable to process a respective vertex pair of an input scan line to generate an output scan line. Each bit inverter is operable to invert a respective input bit of the input scan line to generate a respective output bit of the output scan line if a bit position is located between the respective vertex pair, otherwise the respective input bit is copied to the respective output bit. The instructions correspond to the output bits for each beam.Type: GrantFiled: March 22, 2010Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Faruk Krecinic, Shy-Jay Lin, Jeng-Horng Chen, Shih-Ming Chang, Tuane Ying Fang, Wei-Long Wang, Chien-Hsun Chen
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Publication number: 20130014897Abstract: An apparatus for controlling a plasma etching process includes plasma control structure that can vary a size of a plasma flow passage, vary a speed of plasma flowing through the plasma flow passage, vary plasma concentration flowing through the plasma flow passage, or a combination thereof.Type: ApplicationFiled: September 21, 2012Publication date: January 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Ming Chang, Chi-Lun Lu
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Publication number: 20120295185Abstract: A hologram reticle and method of patterning a target. A layout pattern for an image to be transferred to a target is converted into a holographic representation of the image. A hologram reticle is manufactured that includes the holographic representation. The hologram reticle is then used to pattern the target. Three-dimensional patterns may be formed in a photoresist layer of the target in a single patterning step. These three-dimensional patterns may be filled to form three-dimensional structures or else used in a multi-surface imaging composition. The holographic representation of the image may also be transferred to a top photoresist layer of a top surface imaging (TSI) semiconductor device, either directly or using the hologram reticle. The top photoresist layer may then be used to pattern an underlying photoresist layer with the image. The lower photoresist layer is used to pattern a material layer of the device.Type: ApplicationFiled: July 20, 2012Publication date: November 22, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Ming Chang, Chung-Hsing Chang, Wen-Chuan Wang, Chi-Lun Lu, Sheng-Chi Chin, Chin-Hsiang Lin, Chun-Kuang Chen
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Patent number: 8282850Abstract: An apparatus for controlling a plasma etching process includes plasma control structure that can vary a size of a plasma flow passage, vary a speed of plasma flowing through the plasma flow passage, vary plasma concentration flowing through the plasma flow passage, or a combination thereof.Type: GrantFiled: January 19, 2007Date of Patent: October 9, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Ming Chang, Chi-Lun Lu
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Patent number: 8227150Abstract: A hologram reticle and method of patterning a target. A layout pattern for an image to be transferred to a target is converted into a holographic representation of the image. A hologram reticle is manufactured that includes the holographic representation. The hologram reticle is then used to pattern the target. Three-dimensional patterns may be formed in a photoresist layer of the target in a single patterning step. These three-dimensional patterns may be filled to form three-dimensional structures or else used in a multi-surface imaging composition. The holographic representation of the image may also be transferred to a top photoresist layer of a top surface imaging (TSI) semiconductor device, either directly or using the hologram reticle. The top photoresist layer may then be used to pattern an underlying photoresist layer with the image. The lower photoresist layer is used to pattern a material layer of the device.Type: GrantFiled: April 27, 2010Date of Patent: July 24, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ming Chang, Chung-Hsing Chang, Wen-Chuan Wang, Chi-Lun Lu, Sheng-Chi Chin, Chin-Hsiang Lin, Chun-Kuang Chen