Patents by Inventor Shih-Ping Lee

Shih-Ping Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210223441
    Abstract: A micro-lens structure includes a substrate and a micro-lens. The micro-lens includes a shape adjustment portion and a lens pattern. The shape adjustment portion includes a plurality of shape adjustment patterns on the substrate. The lens pattern covers the shape adjustment patterns.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 22, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Liang Chen, Ya-Ting Chen, Shih-Ping Lee
  • Patent number: 11069715
    Abstract: A memory structure including a SOI substrate, a first transistor, a second transistor, an isolation structure and a capacitor is provided. The SOI substrate includes a silicon base, a dielectric layer and a silicon layer. The first transistor and the second transistor are disposed on the silicon layer. The isolation structure is disposed in the silicon layer between the first transistor and the second transistor. The capacitor is disposed between the first transistor and the second transistor. The capacitor includes a body portion, a first extension portion, a second extension portion and a third extension portion. The first extension portion extends from the body portion to a source/drain region of the first transistor. The second extension portion extends from the body portion to a source/drain region of the second transistor. The third extension portion extends from the body portion, penetrates through the isolation structure and extends into the dielectric layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shyng-Yeuan Che, Shih-Ping Lee
  • Publication number: 20210217792
    Abstract: An image sensor structure including a substrate, a light sensing device, a filter structure, and a separation wall is provided. The light sensing device is located in the substrate. The filter structure is located above the light sensing device. The filter structure includes a main filter layer and a first subordinate filter layer. The separation wall surrounds a sidewall of the filter structure. A refractive index of the filter structure is greater than a refractive index of the separation wall.
    Type: Application
    Filed: February 10, 2020
    Publication date: July 15, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Liang Chen, Chin-Te Huang, Shih-Ping Lee
  • Publication number: 20210129356
    Abstract: A robot arm including a first joint, a second joint, and a coupling element is provided. The first joint has a first inclined surface. The second joint is jointed to the first joint and has a second inclined surface. The coupling element has a third inclined surface and a fourth inclined surface opposite to the third inclined surface, wherein the third inclined surface contacts the first inclined surface, and the fourth inclined surface contacts the second inclined surface.
    Type: Application
    Filed: August 10, 2020
    Publication date: May 6, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Ping LEE, Hen-Diong KNG, Hao-Yan WU, Tsang-Fang JENG, Shu HUANG, Hung-Hsiu YU
  • Publication number: 20210134864
    Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.
    Type: Application
    Filed: January 11, 2021
    Publication date: May 6, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Patent number: 10937819
    Abstract: An image sensor including a substrate, a light sensing device, a storage node, a buried gate structure, and a first light shielding layer is provided. The light sensing device is disposed in the substrate. The storage node is disposed in the substrate. The storage node and the light sensing device are separated from each other. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. The first light shielding layer is disposed on the buried gate and is located above the storage node. The first light shielding layer is electrically connected to the buried gate.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: March 2, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Publication number: 20210043633
    Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 11, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
  • Publication number: 20210035980
    Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 4, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
  • Patent number: 10868017
    Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion and a dummy portion. The circuit portion is electrically connected to the first and second transistors. The dummy portion is located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: December 15, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
  • Patent number: 10861858
    Abstract: A static random-access memory structure includes a substrate, a first conductive type transistor, a second conductive type transistor and a capacitor unit. The first conductive type transistor and the second conductive type transistor are disposed on the surface of the substrate, and the capacitor unit is positioned between the transistors. The capacitor unit includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode includes a plurality of first protrudent portions and a planar portion. The first protrudent portions are connected to the first planar portion and protrude from the top surface of the planar portion. The second electrode covers the top surface of the first protrudent portions and formed between adjacent first protrudent portions.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: December 8, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Yu-Cheng Lu, Kuo-Fang Huang, Chia-Hsien Kuo
  • Publication number: 20200357801
    Abstract: A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.
    Type: Application
    Filed: July 12, 2019
    Publication date: November 12, 2020
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Yu-An Chen, Shih-Siang Chen, Shih-Ping Lee, Yi-Nung Lin, Po-Yi Wu, Chen-Tso Han, Bo-An Tsai
  • Patent number: 10773791
    Abstract: An aircraft with stealth double wings comprises a main body and stealth double wings. The main body has two main wings respectively having a surface into which a space is formed. The stealth double wings respectively are located in the spaces and include a first and a second rotating shaft, a link rod, a first and a second wing. The link rod has two ends respectively connected with the two rotating shafts. The two rotating shafts respectively have another end connected with the first and second wings. Thereby, when the first wing is moved to cover and enclose the space's opening, the second wing is driven to be located within the space, and when the first wing is moved upwardly away from the space, the second wing is driven to cover and enclose the space's opening, so as to keep the surface intact.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: September 15, 2020
    Inventor: Shih-Ping Lee
  • Publication number: 20200235102
    Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion and a dummy portion. The circuit portion is electrically connected to the first and second transistors. The dummy portion is located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 23, 2020
    Applicant: Powerchip Technology Corporation
    Inventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
  • Publication number: 20200227444
    Abstract: A memory structure including a SOI substrate, a first transistor, a second transistor, an isolation structure and a capacitor is provided. The SOI substrate includes a silicon base, a dielectric layer and a silicon layer. The first transistor and the second transistor are disposed on the silicon layer. The isolation structure is disposed in the silicon layer between the first transistor and the second transistor. The capacitor is disposed between the first transistor and the second transistor. The capacitor includes a body portion, a first extension portion, a second extension portion and a third extension portion. The first extension portion extends from the body portion to a source/drain region of the first transistor. The second extension portion extends from the body portion to a source/drain region of the second transistor. The third extension portion extends from the body portion, penetrates through the isolation structure and extends into the dielectric layer.
    Type: Application
    Filed: February 26, 2019
    Publication date: July 16, 2020
    Applicant: Powerchip Technology Corporation
    Inventors: Shyng-Yeuan Che, Shih-Ping Lee
  • Publication number: 20200219891
    Abstract: A static random-access memory structure includes a substrate, a first conductive type transistor, a second conductive type transistor and a capacitor unit. The first conductive type transistor and the second conductive type transistor are disposed on the surface of the substrate, and the capacitor unit is positioned between the transistors. The capacitor unit includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode includes a plurality of first protrudent portions and a planar portion. The first protrudent portions are connected to the first planar portion and protrude from the top surface of the planar portion. The second electrode covers the top surface of the first protrudent portions and formed between adjacent first protrudent portions.
    Type: Application
    Filed: April 25, 2019
    Publication date: July 9, 2020
    Inventors: Shih-Ping Lee, Yu-Cheng Lu, Kuo-Fang Huang, Chia-Hsien Kuo
  • Publication number: 20200075648
    Abstract: An image sensor including a substrate, a light sensing device, a storage node, a buried gate structure, and a first light shielding layer is provided. The light sensing device is disposed in the substrate. The storage node is disposed in the substrate. The storage node and the light sensing device are separated from each other. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. The first light shielding layer is disposed on the buried gate and is located above the storage node. The first light shielding layer is electrically connected to the buried gate.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 5, 2020
    Applicant: Powerchip Technology Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Publication number: 20200031452
    Abstract: An aircraft with stealth double wings comprises a main body and stealth double wings. The main body has two main wings respectively having a surface into which a space is formed. The stealth double wings respectively are located in the spaces and include a first and a second rotating shaft, a link rod, a first and a second wing. The link rod has two ends respectively connected with the two rotating shafts. The two rotating shafts respectively have another end connected with the first and second wings. Thereby, when the first wing is moved to cover and enclose the space's opening, the second wing is driven to be located within the space, and when the first wing is moved upwardly away from the space, the second wing is driven to cover and enclose the space's opening, so as to keep the surface intact.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Inventor: Shih-Ping LEE
  • Patent number: 10094096
    Abstract: A water storage tank built for a reverse osmosis water purifying system deploys multi water flow passages of purified water and drainage water, allocated a soft bladder unit receiving purified water encompassed by the waste water in the tank. When the water tank unit is fully filled with water, the water pressure activates the auto-shut-off valve or solenoid valve to stop operation of the reverse osmosis water purifying system. When the dispensing faucet is turned on, the drainage water swells to squeeze the soft bladder unit to deliver the purified water out from the soft bladder unit to the dispensing faucet, and the drainage water flushes the reverse osmosis membrane as well. The technique enables the tank to take the least water pressure resistance to hold water and drain water which results in energy saving and water saving.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 9, 2018
    Assignee: Maxtec Plastics, Inc.
    Inventor: Shih Ping Lee
  • Patent number: 9899436
    Abstract: An image sensor includes a semiconductor substrate with at least one recess disposed on its surface and in the photosensitive area defined on the surface of the semiconductor substrate, a first-conductivity-type doped region disposed in the semiconductor substrate and in the photosensitive area, and a second-conductivity-type doped region disposed on the surface of the first-conductivity-type doped region and on the surface of the recess. A photosensitive device of the image sensor is formed of the first-conductivity-type doped region and the second-conductivity-type doped region.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 20, 2018
    Assignee: Powerchip Technology Corporation
    Inventors: Shih-Ping Lee, Yu-An Chen, Hsiu-Wen Huang, Chuan-Hua Chang
  • Publication number: 20180040651
    Abstract: An image sensor includes a semiconductor substrate with at least one recess disposed on its surface and in the photosensitive area defined on the surface of the semiconductor substrate, a first-conductivity-type doped region disposed in the semiconductor substrate and in the photosensitive area, and a second-conductivity-type doped region disposed on the surface of the first-conductivity-type doped region and on the surface of the recess. A photosensitive device of the image sensor is formed of the first-conductivity-type doped region and the second-conductivity-type doped region.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 8, 2018
    Inventors: Shih-Ping Lee, Yu-An Chen, Hsiu-Wen Huang, Chuan-Hua Chang