Abstract: The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.

Abstract: A semiconductor device includes a first plurality of channel layers. The first plurality of channel layers extend along a first direction. The semiconductor device includes a second plurality of channel layers. The second plurality of channel layers also extend along the first direction. The semiconductor de123329-vice includes a first dielectric fin structure that also extends along the first direction. The semiconductor device includes a first gate structure that extends along a second direction. The first gate structure comprises a first portion that wraps around each of the first plurality of channel layers and a second portion that wraps around each of the second plurality of channel layers. The first dielectric fin structure separates the first and second portions from each other. The first gate structure comprises a third portion that connects the first and second portions to each other and is vertically disposed below the first dielectric fin structure.

Abstract: A method includes forming a first, second, third, fourth, fifth, and sixth fin structure. The second fin structure is separated from each of the first and third fin structures by a first distance, the fifth fin structure is separated from each of the fourth and sixth fin structures by the first distance, and the third fin structure is separated from the fourth fin structure by a second distance greater than the first distance. The method includes forming a first dummy gate structure overlaying the first through third fin structures, and a second dummy gate structure overlaying the fourth through sixth fin structures; forming a number of source/drain structures that are coupled to the first, second, third, fourth, fifth, and sixth fin structures, respectively; and replacing the third fin structure with a first dielectric structure, and replacing the fourth fin structure with a second dielectric structure.

Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.

Abstract: A low numerical aperture fiber output diode laser module, which having several independent diode lasers, and collimated and converged the light beam, for the coupling the light to the core optical fiber with a core diameter of 105 um and a numerical aperture of 0.12. Compared with general products with a numerical aperture of 0.22, the light output angle is reduced to 55%, and use a general blue laser diode for verification. Use an optical software for facilitating the design and optimization of the parameters of the optical lens module.

Abstract: The present invention provides a human CD16+ natural killer cell line and a CAR-expressing human CD16+ natural killer cell line. These human CD16+ natural killer cell line and a CAR-expressing human CD16+ natural killer cell line does not include synthetic, genetically modified or purposely deliberately delivered polynucleotide encoding the CD16 receptor and are non-tumorigenic cell lines. Therefore, this human CD16+ natural killer cell line and a CAR-expressing human CD16+ natural killer cell line might provide considerable long-term safety for disease treatment.

Abstract: The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.

Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A robot arm including a first joint, a second joint, and a coupling element is provided. The first joint has a first inclined surface. The second joint is jointed to the first joint and has a second inclined surface. The coupling element has a third inclined surface and a fourth inclined surface opposite to the third inclined surface, wherein the third inclined surface contacts the first inclined surface, and the fourth inclined surface contacts the second inclined surface.

Abstract: A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.

Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: An edge ring, for a plasma etcher, may include a circular bottom portion with an opening sized to receive an electrostatic chuck supporting a semiconductor device, and a circular top portion integrally connected to a first top part of the circular bottom portion. The edge ring may include a circular chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion. The circular chamfer portion may include an inner surface that is angled radially outward from the opening at less than ninety degrees.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: A method of fabricating a solid-state image sensor, including steps of forming a second type doped semiconductor layer and a semiconductor material layer sequentially on a first type doped semiconductor substrate to constitute a photoelectric conversion portion, forming a multilayer structure on the semiconductor material layer, wherein a refractive index of the multilayer structure gradually decreases from a bottom layer to a top layer of the multilayer structure and is smaller than a refractive index of the semiconductor material layer, and performing a photolithography process to the multiplayer structure and the photoelectric conversion portion to form multiple micro pillars, wherein the micro pillars protrude from the semiconductor material layer and are isolated by recesses extending into the photoelectric conversion portion.

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A die includes: a semiconductor substrate having a front side and an opposing backside; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the backside of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

Abstract: A solid-state image sensor with pixels each including a photoelectric conversion portion made of a second type doped semiconductor layer and a semiconductor material layer, and the second type doped semiconductor layer contacts a first type doped semiconductor substrate. An anti-reflective portion is provided with multiple micro pillars on the semiconductor material layer, wherein micro pillars are isolated by recesses extending into the photoelectric conversion portion, and the refractive index of the micro pillar gradually decreases from bottom to top and is smaller than the refractive index of the light-receiving portion of the semiconductor material layer.

Abstract: An edge ring, for a plasma etcher, may include a circular bottom portion with an opening sized to receive an electrostatic chuck supporting a semiconductor device, and a circular top portion integrally connected to a first top part of the circular bottom portion. The edge ring may include a circular chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion. The circular chamfer portion may include an inner surface that is angled radially outward from the opening at less than ninety degrees.