Patents by Inventor Shih-Tse Hsu

Shih-Tse Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Failure test method for split gate flash memory
    Patent number: 7050344
    Abstract: A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first bit map of the sector. After being erased, these memory cells in the sector undergo a second read operation to generate a second bit map of the sector. The first bit map and the second bit map are overlaid to identify the actual address of the failed memory cell.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: May 23, 2006
    Assignee: ProMOS Technologies Inc.
    Inventors: Chih-Hung Cho, Ming-Shiahn Tsai, Shih-Tse Hsu, Lih-Wei Lin
  • FAILURE TEST METHOD FOR SPLIT GATE FLASH MEMORY
    Publication number: 20060098505
    Abstract: A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first bit map of the sector. After being erased, these memory cells in the sector undergo a second read operation to generate a second bit map of the sector. The first bit map and the second bit map are overlaid to identify the actual address of the failed memory cell.
    Type: Application
    Filed: November 4, 2004
    Publication date: May 11, 2006
    Inventors: Chih-Hung Cho, Ming-Shiahn Tsai, Shih-Tse Hsu, Lih-Wei Lin