Patents by Inventor Shih-Wei Liang
Shih-Wei Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8692378Abstract: A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.Type: GrantFiled: December 6, 2011Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Ying-Ju Chen, Shih-Wei Liang
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Publication number: 20140091437Abstract: A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer.Type: ApplicationFiled: December 9, 2013Publication date: April 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ying YANG, Hsien-Wei CHEN, Tsung-Yuan YU, Shih-Wei LIANG
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Publication number: 20140077369Abstract: Packaging devices and packaging methods are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming a plurality of through-substrate vias (TSVs) in an interposer substrate. The interposer substrate is recessed or a thickness of the plurality of TSVs is increased to expose portions of the plurality of TSVs. A conductive ball is coupled to the exposed portion of each of the plurality of TSVs.Type: ApplicationFiled: September 20, 2012Publication date: March 20, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-che Ho, Yi-Wen Wu
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Patent number: 8664768Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.Type: GrantFiled: May 3, 2012Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Kai Liu, Chia-Chun Miao, Chun-Lin Lu
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Publication number: 20140045326Abstract: A method of making a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, the semiconductor substrate having a first region and a second region, wherein the first region is a conductive pad and the second region is adjacent to the first region. The method further includes forming a first protective layer overlying the passivation layer and forming an interconnect layer overlying the first protective layer. The method further includes forming a plurality of slots in the second region and forming a second protective layer overlying the interconnect layer, wherein the second protective layer fills each slot of the plurality of slots. The method further includes exposing a portion of the interconnect layer through the second protective layer; forming a barrier layer on the exposed portion of the interconnect layer; and forming a solder bump on the barrier layer.Type: ApplicationFiled: October 21, 2013Publication date: February 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Wei LIANG, Hsien-Wei CHEN, Ying-Ju CHEN, Tsung-Yuan YU, Mirng-Ji LII
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Patent number: 8624359Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.Type: GrantFiled: October 5, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ying Yang, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
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Patent number: 8618827Abstract: Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.Type: GrantFiled: October 13, 2010Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Liang Shao, Shih-Wei Liang, Ying-Ju Chen, Ching-Jung Yang, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
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Patent number: 8581400Abstract: A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.Type: GrantFiled: October 13, 2011Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Liang, Hsien-Wei Chen, Ying-Ju Chen, Tsung-Yuan Yu, Mirng-Ji Lii
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Publication number: 20130292830Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.Type: ApplicationFiled: May 3, 2012Publication date: November 7, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Kai Liu, Chia-Chun Miao, Chun-Lin Lu
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Publication number: 20130292831Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.Type: ApplicationFiled: May 3, 2012Publication date: November 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Kai Liu, Shih-Wei Liang, Hsien-Wei Chen, Kai-Chiang Wu
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Publication number: 20130228897Abstract: Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Shih-Wei Liang
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Publication number: 20130140706Abstract: A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Ying-Ju Chen, Shih-Wei Liang
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Publication number: 20130113097Abstract: In a method of improving ball strength of a semiconductor device, a ball pattern of a plurality of connection balls to be formed as electrical connections for the semiconductor device is received. The pattern includes a number of columns and rows crossing each other. The balls are arranged at intersections of the columns and rows. An arrangement of balls in a region of the ball pattern is modified so that the region includes no isolated balls.Type: ApplicationFiled: November 8, 2011Publication date: May 9, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Yuan YU, Hsien-Wei CHEN, Ying-Ju CHEN, Shih-Wei LIANG
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Publication number: 20130093077Abstract: A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Wei LIANG, Hsien-Wei CHEN, Ying-Ju CHEN, Tsung-Yuan YU, Mirng-Ji LII
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Publication number: 20130087914Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.Type: ApplicationFiled: October 5, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ying YANG, Hsien-Wei CHEN, Tsung-Yuan YU, Shih-Wei LIANG
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Publication number: 20130043598Abstract: Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced.Type: ApplicationFiled: August 18, 2011Publication date: February 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Ju CHEN, Hsien-Wei CHEN, Tsung-Yuan YU, Shih-Wei LIANG
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Publication number: 20120261662Abstract: An integrated circuit system comprising a first integrated and at least one of a second integrated circuit, interposer or printed circuit board. The first integrated circuit further comprising a wiring stack, bond pads electrically connected to the wiring stack, and bump balls formed on the bond pads. First portions of the wiring stack and the bond pads form a functional circuit, and second portions of the wiring stack and the bond pads form a test circuit. A portion of the bump balls comprising dummy bump balls. The dummy bump balls electrically connected to the second portions of the wiring stack and the bond pads. The at least one of the second integrated circuit, interposer orprinted circuit board forming a portion of the test circuit.Type: ApplicationFiled: April 13, 2011Publication date: October 18, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Wei LIANG, Yu-Wen LIU, Hsien-Wei CHEN
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Patent number: 8237160Abstract: A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure.Type: GrantFiled: August 4, 2011Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Chung-Ying Yang, Ying-Ju Chen, Shih-Wei Liang, Ching-Jung Yang
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Publication number: 20120092033Abstract: Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.Type: ApplicationFiled: October 13, 2010Publication date: April 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tung-Liang Shao, Shih-Wei Liang, Ying-Ju Chen, Ching-Jung Yang, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
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Publication number: 20110284843Abstract: A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure.Type: ApplicationFiled: August 4, 2011Publication date: November 24, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Chung-Ying Yang, Ying-Ju Chen, Shih-Wei Liang, Ching-Jung Yang