Abstract: Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.

Abstract: A semiconductor device includes a substrate comprising a front surface, side surfaces, a back surface, and a recessed edge between the side surfaces and either the front surface or the back surface, the front surface comprising an active region, the active region comprising at least one contact pad, a polymeric member disposed and contacted with the recessed edge of the substrate, a mold disposed over the front surface of the substrate and the polymeric member, and an interface between the mold and the polymeric member.

Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace.

Abstract: Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.

Abstract: In some embodiments in accordance with the present disclosure, a semiconductor device including a semiconductor substrate is received. An interconnect structure is provided over the semiconductor substrate, and a passivation is provided over the interconnect structure. The passivation includes an opening such that a portion of the interconnect structure is exposed. Moreover, a dielectric is provided over the passivation, and a post-passivation interconnect (PPI) is provided over the dielectric. The PPI is configured to connect with the exposed portion of the interconnect structure through an opening in the dielectric. Furthermore, the PPI includes a receiving area for receiving a conductor, and a trench adjacent to the receiving area. In certain embodiments, the receiving area is defined by the trench.

Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor device has a metal structure over the semiconductor substrate. The metal structure is configured to receive a bump. The semiconductor device further has a conductive trace between the semiconductor substrate and the metal structure. The conductive trace is configured to connect to a power source. When an electric current from the power source passes through the conductive trace, an electromagnetic field is generated at the conductive trace. The position of the bump is adjusted in response to the electromagnetic field.

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Abstract: A semiconductor structure includes a die including a first surface, a recess extended from an aperture disposed on the first surface and including a sidewall disposed within the die, and a polymeric member configured for filling and sealing the recess and including a first outer surface and a second outer surface, wherein the first outer surface is interfaced with the sidewall of the recess.

Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

Abstract: A method of manufacturing a packaging device may include: forming a plurality of through-substrate vias (TSVs) in a substrate, wherein each of the plurality of TSVs has a protruding portion extending away from a major surface of the substrate. A seed layer may be forming over the protruding portions of the plurality of TSVs, and a conductive ball may be coupled to the seed layer and the protruding portion of each of the plurality of TSVs. The seed layer and the protruding portion of each of the plurality of TSVs may extend into an interior region of the conductive ball.

Abstract: A package comprises a semiconductor device. The semiconductor device comprises an active surface and side surfaces. The active surface has a contact pad. The package also comprises a mold covering the side surfaces of the semiconductor device. The package further comprises an interconnection line coupled with the contact pad and extending over the active surface of the semiconductor device. The package additionally comprises an under-bump metallurgy (UBM) layer over the interconnection line. The package also comprises a seal ring structure extending around and outside an upper periphery of the semiconductor device on the mold, the seal ring structure comprising a seal layer extending on a same level as at least one of the interconnection line or the UBM layer.

Abstract: A semiconductor structure includes a conductive bump for disposing over a substrate and an elongated ferromagnetic member surrounded by the conductive bump, including a first end and a second end, and extending from the first end to the second end, the elongated ferromagnetic member is disposed substantially orthogonal to the substrate to dispose the conductive bump at a predetermined orientation and at a predetermined position of the substrate. Further, a method of manufacturing a semiconductor structure includes providing a substrate, forming a conductive trace within the substrate, applying an electric current passing through the conductive trace to generate an electromagnetic field and disposing a conductive bump including an elongated ferromagnetic member in a predetermined orientation and at a predetermined position above the substrate in response to the electromagnetic field generated by the conductive trace.

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Abstract: A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Abstract: A singulated semiconductor structure comprises a molding compound; a first conductive post in the molding compound having a first geometric shape in a top view; a second conductive post or an alignment mark in the molding compound having a second geometric shape in a top view, wherein the second geometric shape is different from the first geometric shape. The second conductive post or an alignment mark can be positioned at the corner, the center, the edge, or the periphery of the singulated semiconductor structure. The second geometric shape can be any geometric construct distinguishable from the first geometric shape. The second conductive post or an alignment mark can be placed at an active area or a non-active area of the singulated semiconductor structure.

Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor device has a metal structure over the semiconductor substrate. The metal structure is configured to receive a bump. The semiconductor device further has a conductive trace between the semiconductor substrate and the metal structure. The conductive trace is configured to connect to a power source. When an electric current from the power source passes through the conductive trace, an electromagnetic field is generated at the conductive trace. The position of the bump is adjusted in response to the electromagnetic field.

Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace.

Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Abstract: Packaging devices and packaging methods are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming a plurality of through-substrate vias (TSVs) in an interposer substrate. The interposer substrate is recessed or a thickness of the plurality of TSVs is increased to expose portions of the plurality of TSVs. A conductive ball is coupled to the exposed portion of each of the plurality of TSVs.

Abstract: A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.