Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a target layer over a substrate and forming a seed layer over the target layer. The method includes forming a hard mask layer over the seed layer, and the hard mask layer includes an opening to expose a portion of the seed layer. The method includes forming a conductive layer in the opening, and the conductive layer is selectively formed on the portion of the seed layer. The method includes etching a portion of the target layer by using the conductive layer as a mask.

Abstract: A low dropout regulator includes a PMOS power transistor, a feedback network, an error amplifier and an active enhanced PSRR unit. The PMOS power transistor has a first end coupled to an input voltage, and a second end coupled to a load and the feedback network. The error amplifier receives a feedback signal generated from the feedback network, compares the feedback signal with a reference voltage to generate a difference value, and amplifies the difference value to generate an error signal. The active enhanced PSRR unit has one end coupled to the first end, and another end coupled to a control end of the PMOS power transistor and the error amplifier, detects an input voltage of the first end, and correspondingly adjusts a voltage of the control end to stabilize a voltage between the control end and the first end according to a variation of the input voltage.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a FinFET (Field-Effect Transistor) device is provided. Then, spacers and various mask layers are formed on gate structures of the FinFET device to provide a self-alignment structure. Thereafter, source/drain contacts and gate contacts are formed in the self-alignment structure to enable the source/drain contacts to be electrically connected to the source/drain structures of the FinFET device, and enable the gate contacts to be electrically connected to the gate structures. Therefore, self-alignment is achieved.

Abstract: An impedance matching circuit includes a variable impedance circuit, a reference voltage generating circuit and a control circuit. The variable impedance circuit is configured for coupling to a load having an impedance and has a variable impedance; the reference voltage generating circuit coupled to the variable impedance circuit is configured to receive an input voltage of the variable impedance circuit to generate a reference voltage; and the control circuit coupled to the variable impedance circuit and configured to generate a control signal according to the reference voltage and an output voltage of the variable impedance circuit to control the variable impedance to make the variable impedance match the impedance of the load.

Abstract: A power supply system and a power supply method are provided. The power supply system includes a target device, a power supplier module and a control circuit. The control circuit is coupled to the target device and the power supplier module. The control circuit transmits a power provided by the power supplier module to the target device and disables a sub-target device of the target device if the power supplier module does not meet a default condition. The control circuit transmits the power provided by the power supplier module to the target device and enables the sub-target device if the power supplier module meets the default condition.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a FinFET (Field-Effect Transistor) device is provided. Then, spacers and various mask layers are formed on gate structures of the FinFET device to provide a self-alignment structure. Thereafter, source/drain contacts and gate contacts are formed in the self-alignment structure to enable the source/drain contacts to be electrically connected to the source/drain structures of the FinFET device, and enable the gate contacts to be electrically connected to the gate structures. Therefore, self-alignment is achieved.

Abstract: A method for estimating cable length in an Ethernet system and a receiver thereof are applicable to an Ethernet system. The method for estimating cable length includes obtaining a channel tap from channel information of a feedback equalizer in the Ethernet system and estimating a cable length according to the channel tap, a first coefficient and a constant.

Abstract: A biasing voltage generating circuit for generating a required reverse biasing voltage of an avalanche photodiode (APD) includes: a boost power converter configured to operably convert an input voltage into a higher output voltage according to a feedback signal and a reference signal, and to apply the output voltage to be a reverse biasing voltage of the APD; a reference signal generating circuit configured to operably generate the reference signal; and a control circuit. The control circuit includes: a signal sensing circuit configured to operably generate a sensed signal corresponding to an output current of the APD; an analog-to-digital converter (ADC) configured to operably convert the sensed signal into a digital signal; and a processing circuit configured to operably adjust the feedback signal or the reference signal according to the digital signal to thereby control the boost power converter to adjust the output voltage.

Abstract: The invention relates to a use of an aurantiamide dipepetide derivative in the treatment or prevention of angiogenesis-related diseases. Accordingly, aurantiamide dipeptide derivatives can be used as angiogenesis inhibitor, whereby preventing or treating invasive and metastatic cancer and ocular neovascularization (particularly macular degeneration such as pathological neovascularization of age-related macular degeneration (AMD)).

Abstract: An operation voltage testing circuit includes a voltage generating circuit, a current-to-voltage conversion circuit, and a processing circuit. The voltage generating circuit is configured to generate a first voltage signal according to a first current signal, such that a photoelectric conversion unit generates a second current signal corresponding to the first voltage signal. The current-to-voltage conversion circuit is configured to generate a second voltage signal corresponding to the second current signal. The processing circuit is configured to receive the second voltage signal and to selectively adjust and output the first current signal according to the second voltage signal and a threshold value, such that the voltage generating circuit selectively adjusts the first voltage signal according to the first current signal.

Abstract: A channel detection method for an echo canceller of a communication device is provided. The method includes the following steps. A first detection signal is transmitted to an end of a channel coupled to the communication device. A plurality of taps corresponding to a reflected signal of the first detection signal are received by an echo canceller at the end of the channel. The taps corresponding to the reflected signal are compared with a reference value corresponding to each of the taps so as to determine whether each of the taps is larger than or equal to the corresponding reference value. When the tap is determined to be larger than or equal to the reference value corresponding to the tap, the tap and a position of the tap are recorded.

Abstract: A low dropout regulator includes a PMOS power transistor, a feedback network, an error amplifier and an active enhanced PSRR unit. The PMOS power transistor has a first end coupled to an input voltage, and a second end coupled to a load and the feedback network. The error amplifier receives a feedback signal generated from the feedback network, compares the feedback signal with a reference voltage to generate a difference value, and amplifies the difference value to generate an error signal. The active enhanced PSRR unit has one end coupled to the first end, and another end coupled to a control end of the PMOS power transistor and the error amplifier, detects an input voltage of the first end, and correspondingly adjusts a voltage of the control end to stabilize a voltage between the control end and the first end according to a variation of the input voltage.

Abstract: A regulator includes a driving circuit, an amplifying circuit and an overvoltage protection circuit. The driving circuit is configured to receive an input voltage and provide an output voltage through an output terminal. The amplifying circuit is configured to control the driving circuit according to the output voltage. The overvoltage protection circuit is configured to conduct a first current from the output terminal of the overprotection circuit to a ground terminal. When the overvoltage protection circuit detects that a voltage level of a node coupled to the driving circuit is increased, the overvoltage protection circuit conducts a second current from the output terminal of the overprotection circuit to the ground terminal to lower the output voltage, in which the second current is larger than the first current.

Abstract: A regulator includes a driving circuit, an amplifying circuit and an overvoltage protection circuit. The driving circuit is configured to receive an input voltage and provide an output voltage through an output terminal. The amplifying circuit is configured to control the driving circuit according to the output voltage. The overvoltage protection circuit is configured to conduct a first current from the output terminal of the overprotection circuit to a ground terminal. When the overvoltage protection circuit detects that a voltage level of a node coupled to the driving circuit is increased, the overvoltage protection circuit conducts a second current from the output terminal of the overprotection circuit to the ground terminal to lower the output voltage, in which the second current is larger than the first current.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a target layer over a substrate and forming a seed layer over the target layer. The method includes forming a hard mask layer over the seed layer, and the hard mask layer includes an opening to expose a portion of the seed layer. The method includes forming a conductive layer in the opening, and the conductive layer is selectively formed on the portion of the seed layer. The method includes etching a portion of the target layer by using the conductive layer as a mask.

Abstract: A regulator includes a driver circuit, an amplifier circuit, a first current source circuit and a second current source circuit. The driver circuit is configured to receive an input voltage and provide an output voltage. The first current source circuit is configured to provide a first current to the amplifier circuit. The second current source circuit is configured to provide a second current to the amplifier circuit according to the output voltage if the output voltage deviates from a predetermined voltage. The amplifier circuit is configured to control the driver circuit according to the output voltage and a third current, in which the third current is a sum of the first current and the second current.

Abstract: The invention relates to a use of an aurantiamide dipepetide derivative in the treatment or prevention of angiogenesis-related diseases. Accordingly, aurantiamide dipeptide derivatives can be used as angiogenesis inhibitor, whereby preventing or treating invasive and metastatic cancer and ocular neovascularization (particularly macular degeneration such as pathological neovascularization of age-related macular degeneration (AMD)).

Abstract: The present invention discloses a temperature insensitive testing device comprising: a transmission-end test sequence generating circuit to generate a test sequence; a transmission circuit to process the test sequence according to a transmission clock and thereby generate a test signal; a reception circuit to process an echo of the test signal and generate a digital echo signal; a correlation-value generating circuit to generate correlation values including a maximum correlation value according to the test sequence and the digital echo signal; and a decision circuit to determine whether a relation between the maximum correlation value and at least one threshold satisfies a predetermined condition and thereby generate a decision result, wherein the frequency of the transmission clock is lower than a predetermined frequency which confines the variation of the maximum correlation value to a predetermined range provided that the temperature variation of the transmission cable is within a temperature variation ran

Abstract: A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer.

Abstract: A transmission line driver circuit includes: a transmission line driving amplifier having a first transmission terminal and a second transmission terminal; a first signal node; a second signal node; a first adjustable resistor positioned between the first transmission terminal and the first signal node; a second adjustable resistor positioned between the second transmission terminal and the second signal node; an internal node; a first divider resistor positioned between the first signal node and the internal node; a second divider resistor positioned between the second signal node and the internal node; a comparing circuit for comparing a divided voltage at the internal node with a reference voltage to generate a comparison signal; and an adjusting circuit for adjusting resistance of at least one of the first and second adjustable resistors according to the comparison signal.