Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: An example computing device includes a first housing portion, a second housing portion moveably connected to the first housing portion, a link to selectively secure the second housing portion to the first housing portion to inhibit movement of the second housing portion relative to the first housing portion, and a shape-memory alloy element to release the link to allow the second housing portion to move relative to the first housing portion.

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

Abstract: A timing calibration system is applicable to a memory read system which includes a memory, a delay unit and a data read circuit. The memory outputs a data signal and a data latch signal. The delay unit delays the data latch signal by a delay value, to generate a read signal. The data read circuit reads the data signal according to the read signal. In the timing calibration system, a logic computation unit generates first and second charging signals according to the data signal and the read signal, and a capacitor-resistor charging unit performs charging operations according to the first and second charging signals, so as to generate first and second capacitor voltages, and a comparing unit can compare the first and second capacitor voltages, to generate a comparison result, thereby adjusting the delay value of the delay unit according to the comparison result.

Abstract: A timing calibration system is applicable to a memory read system which includes a memory, a delay unit and a data read circuit. The memory outputs a data signal and a data latch signal. The delay unit delays the data latch signal by a delay value, to generate a read signal. The data read circuit reads the data signal according to the read signal. In the timing calibration system, a logic computation unit generates first and second charging signals according to the data signal and the read signal, and a capacitor-resistor charging unit performs charging operations according to the first and second charging signals, so as to generate first and second capacitor voltages, and a comparing unit can compare the first and second capacitor voltages, to generate a comparison result, thereby adjusting the delay value of the delay unit according to the comparison result.

Abstract: A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer includes a plurality of insulating layers, the insulating layers have at least one groove, the groove is disposed between the first inner pads and the first outer pads, and the groove surrounds the first inner pads. A plurality of second chips are flipped on the chip bonding regions, so that second conductive bumps are located between and connected to the first inner pads and second pads of the second chips.

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

Abstract: A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer includes a plurality of insulating layers, the insulating layers have at least one groove, the groove is disposed between the first inner pads and the first outer pads, and the groove surrounds the first inner pads. A plurality of second chips are flipped on the chip bonding regions, so that second conductive bumps are located between and connected to the first inner pads and second pads of the second chips.

Abstract: A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.

Abstract: A multi-chip package structure includes a first chip, a second chip, a circuit layer, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip has a chip bonding region, a plurality of first inner pads and first outer pads. The circuit layer is disposed on the first chip and includes a plurality of insulating layers and at least one metal layer. The insulating layers have a groove disposed between the first inner pads and the first outer pads and surrounding the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip bonding region. Each first inner pad is electrically connected to a second pad of the second chip through the second conductive bump. The underfill is disposed between the first and second chips and covers the second conductive bumps.

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

Abstract: A multi-chip package structure includes a first chip, a second chip, a circuit layer, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip has a chip bonding region, a plurality of first inner pads and first outer pads. The circuit layer is disposed on the first chip and includes a plurality of insulating layers and at least one metal layer. The insulating layers have a groove disposed between the first inner pads and the first outer pads and surrounding the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip bonding region. Each first inner pad is electrically connected to a second pad of the second chip through the second conductive bump. The underfill is disposed between the first and second chips and covers the second conductive bumps.

Abstract: A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.

Abstract: A chip package structure includes a lead frame having first and second patterned metal layers and an insulation layer, a chip, and an encapsulant covering the first patterned metal layer and the chip. The first patterned metal layer includes a chip pad with first recesses and bonding pads in the first recesses. A first groove exists between each bonding pad and the chip pad. The second patterned metal layer connecting the first patterned metal layer includes terminal pads and a heat dissipation block thermally coupled to the chip pad. The heat dissipation block includes second recesses where the terminal pads are located and electrically connected to the corresponding bonding pads. A second groove exists between each terminal pad and the heat dissipation block. The insulation layer is located between the bonding pads and the terminal pads. The chip on the chip pad is electrically connected to the bonding pads.

Abstract: A chip package structure includes a lead frame having first and second patterned metal layers and an insulation layer, a chip, and an encapsulant covering the first patterned metal layer and the chip. The first patterned metal layer includes a chip pad with first recesses and bonding pads in the first recesses. A first groove exists between each bonding pad and the chip pad. The second patterned metal layer connecting the first patterned metal layer includes terminal pads and a heat dissipation block thermally coupled to the chip pad. The heat dissipation block includes second recesses where the terminal pads are located and electrically connected to the corresponding bonding pads. A second groove exists between each terminal pad and the heat dissipation block. The insulation layer is located between the bonding pads and the terminal pads. The chip on the chip pad is electrically connected to the bonding pads.

Abstract: A semiconductor package and manufacturing method thereof are disclosed. The semiconductor package includes a package carrier, a chip, a film, a first shielding metal plate and an encapsulating material. The package carrier has at least one conductive component. The chip has an active surface and a corresponding back surface. The back surface of the chip is attached to the package carrier. At least one contact point is disposed on the active surface and is electrically coupled to the conductive component by a wire. The film is disposed on the active surface and covers a portion of the wire. The first shielding metal plate is disposed on the film. The encapsulating material covers the chip, the wire, at least one portion of the package carrier, the film and at least one portion of the first shielding metal plate.

Abstract: An MEMS package and the manufacturing method thereof are disclosed. The MEMS package includes a package substrate, a block ring, an MEMS chip and an encapsulating material. The package substrate has an inner surface, a corresponding outer surface and a signal opening that penetrates the inner surface and outer surface. The package substrate further has at least one inner contact pad and at least one outer contact pad wherein the outer contact pad is disposed on the outer surface. The inner contact pad is electrically coupled to the outer contact pad. The block ring is disposed on the inner surface and surrounds the signal opening. The MEMS chip has an active surface, at least one sensor device and at least one chip contact pad, wherein the sensor device and the chip contact pad are disposed on the active surface. The active surface is attached to the block ring so that the sensor device is surrounded by the block ring. The chip contact pad is electrically coupled to the inner contact pad.

Abstract: A method of manufacturing a semiconductor package structure is provided. A supporting plate and multiple padding patterns on an upper surface of the supporting plate define a containing cavity. Multiple leads electrically insulated from one another are formed on the padding patterns, extend from top surfaces of the padding patterns along side surfaces to the upper surface and are located inside the containing cavity. A chip is mounted inside the containing cavity, electrically connected to the leads. A molding compound is formed to encapsulate at least the chip, a portion of the leads and a portion of the supporting plate, fill the containing cavity and gaps among the padding patterns, and exposes a portion of the leads on the top surface. The supporting plate is removed to expose a back surface of each padding pattern, a bottom surface of the molding compound and a lower surface of each lead.