Abstract: A method for manufacturing a light emitting chip package includes bonding a patterned metal plate having at least a thermal enhanced plate and many contacts around the same to a substrate and bonding a film-like circuit layer to the patterned metal plate. Many conductive wires are formed to connect the film-like circuit layer and the contacts. Thereafter, at least a first molding is formed on the substrate to encapsulate the patterned metal plate, the conductive wires and a portion of the film-like circuit layer. At least one light emitting chip disposed on the film-like circuit layer exposed by the first molding has many bumps to which the light emitting chip and the film-like circuit layer are electrically connected. A cutting process is performed to form at least one light emitting chip package, and the substrate is removed. Therefore, heat dissipation efficiency of the light emitting chip package can be improved.

Abstract: A manufacturing method of a chip package structure is provided. A circuit substrate having a first surface, a second surface, and a through hole connecting the first surface and the second surface is provided. A chip having an active surface and bonding pads disposed on the active surface is provided. The chip is fixed on the circuit substrate, wherein the second surface is opposite to the active surface and the bonding pads are exposed to the through hole. Bonding wires connecting the bonding pads and the first surface are formed through the through hole. A film having an opening is formed on the first surface. The bonding wires, the bonding pads, the through hole, and part of the first surface are exposed by the opening. An encapsulant is formed to encapsulate part of the active surface, the bonding wires, and part of the first surface. The film is removed.

Abstract: A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around the through holes. The chip with an active surface and a plurality of bonding pads on the active surface is disposed on the carrying surface. The active surface is attached to the carrying surface and the through holes expose the bonding pads. The bonding wires go through the through holes to electrically connect with the bonding pads and the contacts. In addition, the shape and size of the molding compound can be adjusted for covering the chip, the contacts, and the bonding wires.

Abstract: A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around the through holes. The chip with an active surface and a plurality of bonding pads on the active surface is disposed on the carrying surface. The active surface is attached to the carrying surface and the through holes expose the bonding pads. The bonding wires go through the through holes to electrically connect with the bonding pads and the contacts. In addition, the shape and size of the molding compound can be adjusted for covering the chip, the contacts, and the bonding wires.

Abstract: A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.

Abstract: A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.

Abstract: A semiconductor chip package comprises a lead frame having a plurality of leads defining a center area, and a die pad located on the center area of the leads and having at least one downward protuberance on the edge of the die pad; a semiconductor chip attached on the die pad and having a plurality of bonding pads located on the active surface thereof; a plurality of bonding wires connecting the leads and the bonding pads of the semiconductor chip; and a package body encapsulating the lead frame, the semiconductor chip and the bonding wires, wherein the at least one protuberance of the die pad of the lead frame is exposed outside the package body.