Patents by Inventor Shih-Wen Liu
Shih-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955338Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.Type: GrantFiled: January 30, 2023Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
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Publication number: 20240087896Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Chih-Min HSIAO, Chien-Wen LAI, Ru-Gun LIU, Chih-Ming LAI, Shih-Ming CHANG, Yung-Sung YEN, Yu-Chen CHANG
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Patent number: 11920157Abstract: Applications of butylidenephthalide (BP), comprising the use of BP in providing a kit for promoting differentiation of stem cells into brown adipose cells, and the use of BP in preparing a medicament, wherein the medicament is used for inhibiting the accumulation of white adipose cells, promoting the conversion of white adipose cells into brown adipose cells, inhibiting weight gain and/or reducing the content of triglycerides, glucose, and total cholesterol in blood.Type: GrantFiled: September 15, 2022Date of Patent: March 5, 2024Assignee: NATIONAL DONG HWA UNIVERSITYInventors: Tzyy-Wen Chiou, Shinn-Zong Lin, Horng-Jyh Harn, Hong-Lin Su, Shih-Ping Liu, Kang-Yun Lu, Jeanne Hsieh
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Patent number: 11244832Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.Type: GrantFiled: July 27, 2020Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Hsiao-Chiu Hsu
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Publication number: 20200388498Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.Type: ApplicationFiled: July 27, 2020Publication date: December 10, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Fu-Kai YANG, Shih-Wen LIU, Hsiao-Chiu HSU
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Patent number: 10790197Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: GrantFiled: December 16, 2019Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
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Patent number: 10727068Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure and forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure. The method further includes forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer and removing the dummy gate structure to form a tube-shaped trench. The method further includes removing a portion of the dielectric layer to form a cone-shaped trench and forming a gate structure in a bottom portion of the tube-shaped trench. The method further includes forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench, and an interface between the hard mask structure and the dielectric layer overlaps the spacer.Type: GrantFiled: October 8, 2019Date of Patent: July 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Hsiao-Chiu Hsu
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Publication number: 20200118884Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: I-Wen WU, Hsien-Cheng WANG, Mei-Yun WANG, Shih-Wen LIU, Chao-Hsun WANG, Yun LEE
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Publication number: 20200051821Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure and forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure. The method further includes forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer and removing the dummy gate structure to form a tube-shaped trench. The method further includes removing a portion of the dielectric layer to form a cone-shaped trench and forming a gate structure in a bottom portion of the tube-shaped trench. The method further includes forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench, and an interface between the hard mask structure and the dielectric layer overlaps the spacer.Type: ApplicationFiled: October 8, 2019Publication date: February 13, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Fu-Kai YANG, Shih-Wen LIU, Hsiao-Chiu HSU
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Patent number: 10510614Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: GrantFiled: April 29, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
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Patent number: 10468257Abstract: Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.Type: GrantFiled: August 18, 2016Date of Patent: November 5, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Audrey Hsiao-Chiu Hsu
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Publication number: 20190252265Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: I-Wen WU, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
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Patent number: 10276448Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: GrantFiled: October 22, 2018Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
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Patent number: 10276437Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.Type: GrantFiled: December 20, 2016Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Audrey Hsiao-Chiu Hsu, Fu-Kai Yang, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsin-Ying Lin
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Publication number: 20190057906Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Inventors: I-Wen WU, Hsien-Cheng WANG, Mei-Yun WANG, Shih-Wen LIU, Chao-Hsun WANG, Yun LEE
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Patent number: 10163703Abstract: A method for forming a self-aligned contact is provided. In an embodiment, a metal gate is formed on a substrate, and a gate spacer is formed adjacent the metal gate. A conductive plug is formed over the substrate, with the gate spacer disposed between the metal gate and the conductive plug. The metal gate and the conductive plug are recessed. A first dielectric layer is deposited over the gate spacer, over the metal gate, over the conductive plug, and along sidewalls of the metal gate. A first opening is formed in the first dielectric layer exposing the metal gate, and a second opening is formed in the first dielectric layer exposing the conductive plug. The first opening and the second opening are filled with a first conductive material.Type: GrantFiled: June 12, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chao-Hsun Wang, Shih-Wen Liu, Fu-Kai Yang, Hsien-Cheng Wang, Mei-Yun Wang
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Patent number: 10109530Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: GrantFiled: September 1, 2017Date of Patent: October 23, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
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Publication number: 20180012807Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: ApplicationFiled: September 1, 2017Publication date: January 11, 2018Inventors: I-Wen WU, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
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Publication number: 20170278751Abstract: Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer.Type: ApplicationFiled: June 12, 2017Publication date: September 28, 2017Inventors: Chao-Hsun Wang, Shih-Wen Liu, Fu-Kai Yang, Hsien-Cheng Wang, Mei-Yun Wang
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Patent number: 9754838Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: GrantFiled: November 28, 2016Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee