Patents by Inventor Shih-Wen Liu

Shih-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150194425
    Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 9, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Wen Wu, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsiao-Chiu Hsu, Hsin-Ying Lin
  • Publication number: 20150179573
    Abstract: A method for manufacturing semiconductor device is provided. The method includes the following operations: providing a first conductive portion, a second conductive portion and a third conductive portion over a substrate; forming a dielectric layer over the first conductive portion, the second conductive portion, and the third conductive portion; forming a high-resistance layer over the first conductive portion; forming an oxide layer over the high-resistance layer and the dielectric layer; patterning the dielectric layer and the oxide layer by using the high-resistance layer as a blocking layer to form a first recess to expose the second conductive portion and the third conductive portion and to prevent the first conductive portion from exposure; and forming a plug layer in the first recess to connect the second conductive portion and the third conductive portion.
    Type: Application
    Filed: December 24, 2013
    Publication date: June 25, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: AUDREY HSIAO-CHIU HSU, FU-KAI YANG, MEI-YUN WANG, HSIEN-CHENG WANG, SHIH-WEN LIU, HSIN-YING LIN
  • Publication number: 20150123213
    Abstract: Embodiments of mechanism for an integrated circuit (IC) structure are provided. The IC structure includes a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The IC structure further includes a gate structure formed over the substrate, and the gate structure extends from the first diffusion region to the second diffusion region. The IC structure further includes a contact formed over the substrate, and the contact includes a wide portion over the first diffusion region and the second diffusion region and a thin portion over the isolation structure.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Shih-Wen LIU, Fu-Kai YANG, Audrey Hsiao-Chiu HSU
  • Publication number: 20150123175
    Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. In addition, a method for forming the semiconductor device structure is also provided.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Fu-Kai YANG, Shih-Wen LIU, Audrey Hsiao-Chiu HSU
  • Patent number: 8362541
    Abstract: A manufacturing method of DRAM is provided. A substrate having a deep trench is provided, and then a deep trench capacitor including a bottom electrode, an upper electrode and a capacitor dielectric layer is formed in the deep trench. A part of the upper electrode of the deep trench capacitor is removed to form a first trench. A buried strap is formed in the substrate on one side of the upper electrode. An isolation structure is formed in the first trench to define an active region. A part of the substrate adjacent to the isolation structure is removed to form a second trench. A first heavily doped region is formed on the bottom of the second trench, and the first heavily doped region is electrically connected to the buried strap. A dielectric layer is formed on the bottom of the second trench.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: January 29, 2013
    Assignee: Nanya Technology Corporation
    Inventor: Shih-Wen Liu
  • Publication number: 20100327551
    Abstract: This invention relates to a bicycle structure which essentially provides a bicycle body enabling stand-riding such that the weight center of human body can be more concentrated between the front wheel and the rear wheel, and that the wheel base between the front wheel and the rear wheel can be shortened. Thus, the volume of the bicycle is further reduced to become more compact and to save cost. Transmission units are provided respectively at both sides of the bottom, which are independently operated and include pedals moving up and down. Freewheels are provided respectively at both sides of the rear wheel of the bicycle body, and the transmission units at both sides are respectively connected to the freewheels. Not only the structure is simple for easy assembly, but also the volume after folding is very small for easy carry. A number of speed change points can also be provided on each transmission unit to increase the stroke of the freewheel so that the goal of speed change can be achieved.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventors: Wan-Chi Liu, Shih-Wen Liu
  • Publication number: 20100203693
    Abstract: A manufacturing method of DRAM is provided. A substrate having a deep trench is provided, and then a deep trench capacitor including a bottom electrode, an upper electrode and a capacitor dielectric layer is formed in the deep trench. A part of the upper electrode of the deep trench capacitor is removed to form a first trench. A buried strap is formed in the substrate on one side of the upper electrode. An isolation structure is formed in the first trench to define an active region. A part of the substrate adjacent to the isolation structure is removed to form a second trench. A first heavily doped region is formed on the bottom of the second trench, and the first heavily doped region is electrically connected to the buried strap. A dielectric layer is formed on the bottom of the second trench.
    Type: Application
    Filed: April 23, 2010
    Publication date: August 12, 2010
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Shih-Wen Liu
  • Patent number: 7732849
    Abstract: A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a vertical transistor, a deep trench capacitor and a buried strap. The substrate has a trench and a deep trench located on one side of the trench thereon. The vertical transistor is disposed in the trench, a portion of which is disposed on the substrate. The deep trench capacitor is disposed in the deep trench, and comprises a bottom electrode, a capacitor dielectric layer and a top electrode. The vertical transistor comprises a gate structure disposed in the trench and above the substrate, a first doped region disposed in the substrate on sidewalls and bottom of the trench, and a second doped region disposed in the substrate on top of the trench. The buried strap is disposed in the substrate below the vertical transistor, and is adjoined to the first doped region and the top electrode.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: June 8, 2010
    Assignee: Nanya Technology Corporation
    Inventor: Shih-Wen Liu
  • Publication number: 20080290389
    Abstract: A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a vertical transistor, a deep trench capacitor and a buried strap. The substrate has a trench and a deep trench located on one side of the trench thereon. The vertical transistor is disposed in the trench, a portion of which is disposed on the substrate. The deep trench capacitor is disposed in the deep trench, and comprises a bottom electrode, a capacitor dielectric layer and a top electrode. The vertical transistor comprises a gate structure disposed in the trench and above the substrate, a first doped region disposed in the substrate on sidewalls and bottom of the trench, and a second doped region disposed in the substrate on top of the trench. The buried strap is disposed in the substrate below the vertical transistor, and is adjoined to the first doped region and the top electrode.
    Type: Application
    Filed: November 9, 2007
    Publication date: November 27, 2008
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Shih-Wen Liu