Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.

Abstract: A mode-swappable tire pressure detection system and a method of operating the same are provided and applied to tires of motor vehicles. The mode-swappable tire pressure detection system has a tire pressure detector. The tire pressure detector has a memory module. The memory module is configured with sensing modes, rendering the tire pressure detector capable of switching between different sensing modes. When a user issues a control instruction to a host or the tire pressure detector, the tire pressure detector can switch between different sensing modes through the memory module.

Abstract: A FinFET device includes a first fin and a second fin on a substrate, a dielectric fin, a metal gate line, a gate dielectric layer, a gate isolation structure. The dielectric fin is located between the first fin and the second fin. The metal gate line is across the first fin, the dielectric fin and the second fin. The gate dielectric layer is located between the metal gate line and the dielectric fin, between the metal gate line and the first fin, and between the metal gate line and the second fin. The gate isolation structure extends through the first metal gate line and the gate dielectric layer, and landing on the dielectric fin. A top surface of the gate dielectric layer is lower than a top surface of the gate isolation structure.

Abstract: A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.

Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.

Abstract: A duplex Bluetooth transmission tire pressure system and a method thereof are provided. The system includes a Bluetooth tire pressure detector and a transceiver host, and the two can duplex Bluetooth transmit to each other, so that to complete locating and tire condition detecting. The transceiver host controls a locating program that controls the Bluetooth tire pressure detector to start or stop and limit the transmitting packet of the tire condition program of the Bluetooth tire pressure detector.

Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.

Abstract: Provided are devices with replacement structures and methods for fabricating such structures. A method includes forming a layer over a semiconductor material having a top surface in a horizontal plane; forming a dummy structure over the layer, wherein the dummy structure has sidewall, wherein the dummy structure lies directly over a first region of the layer and over a first region of the semiconductor material under the first region of the layer, and wherein the dummy structure does not lie directly over a second region of the layer or over a second region of the semiconductor material under the second region of the layer, and removing the second region of the layer and forming a side edge of the first region of the layer, wherein the side edge forms an angle of from 90 to 100 degrees with the horizontal plane.

Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.

Abstract: A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction, the gate structure comprising a first portion and a second portion. A top surface of the dielectric fin is vertically above respective top surfaces of the first and second semiconductor fins. The first portion and the second portion are electrically isolated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

Abstract: In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer is formed on an end of each of the etched first semiconductor layers. One or more epitaxial layers are formed in the source/drain space, and the sacrificial gate structure is replaced with a metal gate structure. A width of the source/drain space at a bottommost one of the first semiconductor layers is greater than a width of the source/drain space at one of the first semiconductor layers above the bottommost one of the first semiconductor layers.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.

Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

Abstract: A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction, the gate structure comprising a first portion and a second portion. A top surface of the dielectric fin is vertically above respective top surfaces of the first and second semiconductor fins. The first portion and the second portion are electrically isolated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.