Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A semiconductor device includes a first plurality of channel layers. The first plurality of channel layers extend along a first direction. The semiconductor device includes a second plurality of channel layers. The second plurality of channel layers also extend along the first direction. The semiconductor de123329-vice includes a first dielectric fin structure that also extends along the first direction. The semiconductor device includes a first gate structure that extends along a second direction. The first gate structure comprises a first portion that wraps around each of the first plurality of channel layers and a second portion that wraps around each of the second plurality of channel layers. The first dielectric fin structure separates the first and second portions from each other. The first gate structure comprises a third portion that connects the first and second portions to each other and is vertically disposed below the first dielectric fin structure.

Abstract: A method for making a semiconductor device includes forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another. The method includes forming a dummy gate structure, over the fin structure, that extends along a second direction perpendicular to the first direction. The method includes forming a gate spacer extending along respective upper sidewall portions of the dummy gate structure, thereby defining a first distance between a bottom surface of the gate spacer and a top surface of a topmost one of the plurality of channel layers. The first distance is either zero or similar to a second distance that separates neighboring ones of the plurality of channel layers.

Abstract: A method, computer program, and computer system are provided for image segmentation. Image data, such as biological image data, is received. One or more objects associated with the received image data is detected. One or more regions of interest are determined within the receive image data corresponding to one or more segments based on the detected objects.

Abstract: A sputtering chamber component including a front surface, a back surface opposite the front surface, and a sputter trap formed on at least a portion of the back surface, and a coating of metallic particles formed on the sputter trap. The coating has a thickness from about 0.025 mm to about 2.54 mm (0.001 inches to about 0.1 inches) and is substantially free of impurities, and the particles of the coating are substantially diffused.

Abstract: A duplex Bluetooth transmission tire pressure system is provided. The duplex Bluetooth transmission tire pressure system includes a host, a plural of Bluetooth tire pressure detectors and a plural of vehicle transceivers; the host is electrically connected to the plural of vehicle transceivers; the plural of vehicle transceivers and the plural of Bluetooth tire pressure detectors are Bluetooth duplex packet transmitted. The plural of Bluetooth tire pressure detectors includes a locating program and a tire condition program. The host commands the vehicle transceiver to transmit a Bluetooth controlling packet to the plural of Bluetooth tire pressure detectors to operate or stop the locating program and limit the tire condition program.

Abstract: A duplex Bluetooth transmission tire pressure system and a method thereof are provided. The system includes a Bluetooth tire pressure detector and a transceiver host, and the two can duplex Bluetooth transmit to each other, so that to complete locating and tire condition detecting. The transceiver host controls a locating program that controls the Bluetooth tire pressure detector to start or stop and limit the transmitting packet of the tire condition program of the Bluetooth tire pressure detector.

Abstract: A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.

Abstract: A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.

Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.

Abstract: A display device includes a display and a transflective module. The transflective module is disposed at one side of the display and includes a glass substrate and a transflective structure layer. The transflective structure layer is disposed on the glass substrate and located between the glass substrate and the display.

Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion. The lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and comprises a first layer and a second layer. The first layer is in contact with a first portion of the sidewall and the second layer is in contact with a second portion of the sidewall.

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate that both extend along a first direction. The method includes forming a dielectric fin extending along the first direction and is disposed between the first and second semiconductor fins. The method includes forming a dummy gate structure extending along a second direction and straddling the first and second semiconductor fins and the dielectric fin. The method includes removing a portion of the dummy gate structure over the dielectric fin to form a trench by performing an etching process that includes a plurality of stages. Each of the plurality of stages includes a combination of anisotropic etching and isotropic etching such that a variation of a distance between respective inner sidewalls of the trench along the second direction is within a threshold.

Abstract: A touch display device includes a flexible substrate, a light emitting structure layer, and a flexible touch sensing layer. The flexible substrate has a first surface and a second surface opposite to each other. The light emitting structure layer is disposed on the first surface of the flexible substrate. The flexible touch sensing layer is disposed on the second surface of the flexible substrate.

Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.