Abstract: A semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. The conductive line and the conductive via are disposed in the single-layered dielectric layer. The conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.

Abstract: A solid composition containing: (a) at least one metal hydride compound; (b) at least one borohydride compound; and (c) at least one of: (i) a transition metal halide, or (ii) a transition metal boride. A “metal hydride” is a compound containing only one metal and hydrogen, including, e.g., alkali and alkaline earth metal hydrides. A “borohydride compound” is a compound containing the borohydride anion, BH4?.

Abstract: A method for estimating internal multiples in seismic data. The method includes selecting a subset from a set of regularly sampled seismic data based on a low-discrepancy point set. The method may then include integrating one or more depth integrals of the inverse-scattering internal multiple prediction (ISIMP) algorithm over each data point in the subset. After integrating the depth integrals, the method may then include integrating a function of the integrated depth integrals using a quasi-Monte Carlo (QMC) integration over the subset, thereby generating an estimate of the internal multiples.

Abstract: A method for production of stabilized fatty acid methyl esters. The method removes unsaturation present in fatty acid methyl esters, or removes unsaturation in triglycerides, which are then transesterified to fatty acid methyl esters.

Abstract: A solid composition containing: (a) at least one metal hydride compound; (b) at least one borohydride compound; and (c) at least one of: (i) a transition metal halide, or (ii) a transition metal boride.

Abstract: A synthetic lubricant comprising a relatively low-molecular-weight acrylic polymer.

Abstract: A heat dissipating device includes a fluid container made of a heat conductive material and having a heat-dissipating wall opposite to a heat-absorbing wall, and a surrounding wall cooperating with the heat-absorbing and heat-dissipating walls so as to confine a sealed vapor chamber. A heat exchanger member is disposed in the vapor chamber, is in heat-conductive contact with the heat-absorbing wall, and contains an amount of working fluid capable of changing into fluid vapor that fills the vapor chamber upon absorbing heat from the heat-absorbing wall. The fluid vapor is capable of changing into fluid condensate when cooled due to contact with the heat-dissipating wall. A heat-conductive cover plate is mounted spacedly on the heat-dissipating wall of the fluid container, and cooperates with the heat-dissipating wall so as to confine a heat-dissipating passage therebetween such that heat absorbed by the heat-dissipating wall is dissipated via the heat-dissipating passage.

Abstract: An additive composition for a metalworking fluid which comprises a reaction product obtainable by the reaction between a molar excess of an anhydride and an amine, wherein the amine is at least one amino alkyl mono- or di- alkanolamine, in particular having a structural formula (I): HOOC—R—CO—NH—X—N(R′)—Y—O—CO—R′′—COOH, wherein: X represents an alkyl group having 1 to 12 carbon atoms, preferably, 2 to 8 carbon atoms and more preferably 3 to 6 carbon atoms; Y represents a hydrocarbyl group having 2 to 12 carbon atoms, preferably 2 to 6 carbon atoms; R′ represents an alkyl or alkanol groups having 2 to 12 carbon atoms; and R and R″ independently represent hydrocarbyl groups which have up to 48 carbon atoms, preferably 2 to 28; more preferably 6 to 13 carbon atoms.

Abstract: A process for producing a bismuth dithiocarbamate or dithiophosphorate by the reaction of a bismuth hydroxide, bismuth oxide or bismuth oxynitrate with a dithiocarbamate or a dithiophosphoric acid. The bismuth dithiocarbamates and dithiophosphorates exhibit very good EP and antiwear properties and are useful in lubricant formulations.

Abstract: A method of fabricating a buried contact. On a substrate having a shallow trench isolation thereon, a gate oxide layer and a polysilicon layer are sequentially formed. The polysilicon layer and the gate oxide layer are patterned to expose a portion of the substrate. A diffusion region is formed in the exposed substrate. On the polysilicon layer and the exposed diffusion region, an amorphous silicon layer is formed. Consequently, a native oxide layer is formed between the polysilicon layer and the amorphous silicon layer, and between the amorphous silicon layer and the diffusion region. An anti-reflection coating layer is formed on the amorphous silicon layer. Using the native oxide layer as an etching buffer, the anti-reflection coating layer and the amorphous silicon layer are patterned until the diffusion region and the polysilicon layer are exposed.

Abstract: A method of fabricating a buried contact. On a substrate having a shallow trench isolation thereon, a gate oxide layer and a polysilicon layer are sequentially formed. The polysilicon layer and the gate oxide layer are patterned to expose a portion of the substrate. A diffusion region is formed in the exposed substrate. On the polysilicon layer and the exposed diffusion region, an amorphous silicon layer is formed. Consequently, a native oxide layer is formed between the polysilicon layer and the amorphous silicon layer, and between the amorphous silicon layer and the diffusion region. An anti-reflection coating layer is formed on the amorphous silicon layer. Using the native oxide layer as an etching buffer, the anti-reflection coating layer and the amorphous silicon layer are patterned until the diffusion region and the polysilicon layer are exposed.

Abstract: A dual gate oxides' process for mixed-mode IC is provided. More particularly, the present invention relates to a dual gate oxides' process for mixed-mode IC, which protects and improves the dual gate oxides' quality.

Abstract: A method for forming transistor devices with different spacer width for mixed-mode IC is provided. The method provides three different kinds of transistor devices on a wafer, two of them have their own spacer with different width, while the remaining one is without a spacer. The method comprises providing a semiconductor substrate having at least a first conductive gate, a second conductive gate and a third conductive gate formed thereon, and forming a first oxide layer over the first conductive gate, the second conductive gate and the third conductive gate. Then, a first etch operation is performed to form an oxide spacer along each sidewall of the first conductive gate, the second conductive gate and the third conductive gate. A first mask is then formed over the first conductive gate, and then the spacer is removed formed along each sidewall of the second conductive gate and the third conductive gate. After that, the first mask over the first conductive gate is removed.

Abstract: A process for forming an adapted small dimension and more quality fabrication is disclosed. One embodiment comprises following: provide a substrate, then form a first dielectric layer and a first photoresist over the substrate. Sequentially, remove partial first dielectric layer until a portion of substrate is exposed. Next, form a first inter-metal dielectric layer over the substrate and treat the first inter-metal dielectric layer by a planarization process. Then, form a second dielectric layer and a second photoresist formed over the first inter-metal dielectric layer. Consequently, remove partial the second dielectric layer until a portion of surface of the first inter-metal dielectric layer is exposed. The, form a second inter-metal dielectric layer over the first inter-metal dielectric layer which followed by a planarization process. Next, remove the second dielectric layer and the first dielectric layer to form a hole.

Abstract: A method of fabricating a static random access memory. A stacked gate is formed on a substrate. A lightly doped drain region and a lightly doped source region are formed in the substrate. A thin spacer is then formed on a sidewall of the stacked gate on the lightly doped source region only. However, this thin spacer does not completely cover the lightly doped source and drain regions, that is, portions of the light doped source and drain regions are exposed. A thick spacer is then formed on the other sidewall of the stacked gate on the lightly doped drain region only. Using both the thin and the thick spacers as a mask, an ion implantation is performed to form a heavily doped source region and a heavily doped drain region in the substrate. A self-aligned silicide step is performed to form a salicide layer on the stacked gate, the source and the drain regions.

Abstract: A method of fabricating a salicide layer in an electrostatic discharge protection device. On a MOS transistor having a gate, a source region and a drain region, a salicide block layer is formed. The salicide layer is patterned to remaining covering the drain region only, and leaving the source region and other portions of the substrate exposed. The anti-reflection coating layer is then removed to expose the gate. A salicide layer is formed on the exposed source region, the gate and other exposed portion of the substrate, while the drain region is free from the salicide layer for being covered with the salicide block layer.

Abstract: A method for forming an adapted small dimension and more quality fabrication is disclosed. In one embodiment, the present invention provides a twin gate CMOS, which includes isolations formed in a semiconductor substrate. A P-well and an N-well inside the semiconductor substrate are formed and isolated by an isolating region. Next, a gate oxide layer and a first polysilicon layer are formed sequentially above the P-well and an N-well. A polysilicon layer doped in-situ with N-type ions. Sequentially, a first oxide layer is deposited and a first photoresist layer is formed on the polysilicon layer above P-well region, wherein etching respective patterns on the first oxide layer and the polysilicon layer. An amorphous silicon layer doped with P-type ions by implanation is formed over the gate oxide layer and the first oxide layer above the semiconductor substrate. After forming a second oxide layer on the amorphous silicon layer.

Abstract: A method of fabricating a load resistor for an SRAM. A substrate has a polysilicon layer formed thereon through a buried contact process. An inter-layer dielectric layer is formed over the substrate and then patterned to form an opening that exposes the polysilicon layer. A poly via is then formed in the opening to serve as a load resistor. The inter-layer dielectric layer is patterned to form a contact window, which is then filled with a conductive layer to form a contact.

Abstract: A method for fabricating a metal interconnect involves forming a first dielectric layer on the substrate having metal lines formed thereon, wherein the top surface of the first dielectric layer is lower than that of the metal line. As a result, the top surface and a part of the sidewall of the metal line are exposed. A spacer is then formed on the exposed sidewall of the metal line. A second dielectric layer is formed on the substrate, wherein the spacer has different etching selectivity from the second dielectric layer. With the spacer serving as an etching stop layer, a via opening is formed in the second dielectric layer, while the via opening is filled with a metal plug to form a via plug.

Abstract: A method for forming a self-align stop layer for borderless contact process is disclosed. In one embodiment, the present invention provides a semiconductor device which can simplify borderless contact fabrication, which includes providing a substrate incorporating a device. Sequentially, a pad oxide, a pad polysilicon, and a first dielectric layer are formed over the substrate. A first photoresist layer is formed over the first dielectric layer and then the first dielectric layer, the pad polysilicon, the pad oxide, and the substrate are etched using the photoresist layer as a mask to form an isolation inside said substrate. Consequentially, a second dielectric layer is deposited over the device and the isolation inside the substrate. The second dielectric layer is removed wherein the surface of the second dielectric layer is lower than the top surface of the substrate by a chemical mechanical polishing (CMP) and etching back.