Patents by Inventor Shih-Yu Wang

Shih-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953839
    Abstract: In a method of cleaning a lithography system, during idle mode, a stream of air is directed, through a first opening, into a chamber of a wafer table of an EUV lithography system. One or more particles is extracted by the directed stream of air from surfaces of one or more wafer chucks in the chamber of the wafer table. The stream of air and the extracted one or more particle are drawn, through a second opening, out of the chamber of the wafer table.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yu Tu, Shao-Hua Wang, Yen-Hao Liu, Chueh-Chi Kuo, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20240100147
    Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).
    Type: Application
    Filed: November 3, 2023
    Publication date: March 28, 2024
    Inventors: Chi-Huey WONG, Hsin-Yu LIAO, Shih-Chi WANG, Yi-An KO, Kuo-I LIN, Che MA, Ting-Jen CHENG
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11921530
    Abstract: A power supply system includes an output terminal, a power supply control chip, a power supply switch and a detection device. The power supply control chip is configured to adjust the amount of an input power providing to an electronic device by the power supply device. The power supply switch is configured to control the connection between the power supply device and the power supply control chip. The detection device is configured to detect whether the power supply control chip operates normally. When the power supply control chip operates abnormally, the detection device controls the connection between the power supply device and the power supply control chip through the power supply switch for restarting the power supply control chip. The power supply control chip, the power supply switch and the detection device are disposed in an enclosed space.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: March 5, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Shih-Chung Wang, Cheng-Yu Shu, Wei-Chieh Lin
  • Patent number: 11918641
    Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 5, 2024
    Assignee: ACADEMIA SINICA
    Inventors: Chi-Huey Wong, Hsin-Yu Liao, Shih-Chi Wang, Yi-An Ko, Kuo-I Lin, Che Ma, Ting-Jen Cheng
  • Publication number: 20240055507
    Abstract: An electrostatic discharge protection circuit includes a N type region, a P type component, a P type region, a N type element, a first conductive terminal, a second conductive terminal, a power clamp circuit and a conductive pad. The P type component is in the N type region. The N type element is in the P type region. The first conductive terminal is electrically connected to the N type region. The second conductive terminal is electrically connected to the P type region and the N type element. The power clamp circuit is electrically connected between the first conductive terminal and the second conductive terminal. The conductive pad is electrically connected to the P type component.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Inventor: Shih-Yu WANG
  • Patent number: 11837600
    Abstract: The electrostatic discharge protection apparatus includes a substrate, a first well having a first conductivity type and disposed in the substrate, a second well having a second conductivity type and disposed in the first well, a first doping region having the first conductivity type and disposed in the second well, a second doping region having the first conductivity type and disposed in the second well, a third doping region having the second conductivity type and disposed in the second well, and a fourth doping region having the first conductivity type and disposed in the substrate. The first conductivity type is different from the second conductivity type. The second well, the first well, the substrate and the fourth doping region form a silicon controlled rectifier. Electrostatic discharge current flowing into the first doping region flows to the fourth doping region through the silicon controlled rectifier.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: December 5, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wen-Tsung Huang, Shih-Yu Wang, Chih-Wei Hsu
  • Publication number: 20230387092
    Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
  • Patent number: 11817449
    Abstract: Methods, systems and apparatus for memory devices with discharging circuits are provided. In one aspect, a semiconductor device includes a semiconductor substrate, one or more discharging circuits arranged on the semiconductor substrate, one or more common source line (CSL) layers conductively coupled to the one or more discharging circuits, and a memory array having a three-dimensional (3D) array of memory cells arranged in a plurality of vertical channels on the one or more CSL layers. Each of the plurality of vertical channels includes a respective string of memory cells, and each of the one or more CSL layers is conductively coupled to corresponding strings of memory cells. Each of the one or more discharging circuits includes one or more transistors that are disabled by one or more corresponding conductive lines through the memory array.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 14, 2023
    Assignee: Macronix International Co., Ltd.
    Inventors: Jung Chuan Ting, Shih-Yu Wang, Shao-Chi Chen
  • Publication number: 20230338924
    Abstract: The invention relates to a stationary phase medium for adsorption chromatography, which is in form of porous particles suitable for being packed into a chromatographic column. The porous particles are made of cross-linked polymeric material and formed with interconnected macropores to constitute a porous network, through which a mobile phase fluid may flow in a convective manner. The porous particles are substantially free of diffusive pores and, thus, the mass transfer through the porous network is governed by convection alone. The porous particles are fabricated to have irregular granular configurations with rough outer surfaces, so that the convective flow between the porous particles will not be impeded during chromatography process.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 26, 2023
    Inventors: Tsung-Han TU, Chia-Wei LIN, Shih-Yu WANG, Hui CHEN, Min-Shyan SHEU, Shih-Horng YANG
  • Patent number: 11791227
    Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuoching Cheng, Yuan-Feng Chiang, Ya Fang Chan, Wen-Long Lu, Shih-Yu Wang
  • Patent number: 11721678
    Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
  • Patent number: 11699745
    Abstract: A thyristor includes a first transistor and a second transistor. The first transistor has a first end serving as an anode end. The second transistor has a control end coupled to a second end of the first transistor, a first end coupled to a control end of the first transistor, and a second end coupled to the first end of the second transistor and serving as a cathode end.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: July 11, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Yu Wang, Wen-Tsung Huang, Chih-Wei Hsu
  • Patent number: 11669046
    Abstract: A display device includes a light source, a waveguide element, a liquid crystal coupler, a first holographic optical element and a second holographic optical element. The light source is configured to emit light. The waveguide element is located above the light source. The liquid crystal coupler is located between the waveguide element and the light source. The first holographic optical element is located on a top surface of the waveguide element, in which the liquid crystal coupler is configured to change an incident angle that the light emits to the first holographic optical element. The second holographic optical element is located on the top surface of the waveguide element, and there is a first distance in a horizontal direction between the first holographic optical element and the second holographic optical element, in which the second holographic optical element is configured to diffract the light to the waveguide element below.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: June 6, 2023
    Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (SingZhen) Co., Ltd., Interface Optoelectronics (Wuxi) Co., Ltd., General Interface Solution Limited
    Inventors: Shih-Yu Wang, Chun-Ta Chen, Shiuan-Huei Lin, Zih-Fan Chen, Wan-Lin Li, Yi-Hsin Lin, Yu-Jen Wang, Wei-Cheng Cheng, Chang-Nien Mao
  • Publication number: 20230154920
    Abstract: The electrostatic discharge protection apparatus includes a substrate, a first well having a first conductivity type and disposed in the substrate, a second well having a second conductivity type and disposed in the first well, a first doping region having the first conductivity type and disposed in the second well, a second doping region having the first conductivity type and disposed in the second well, a third doping region having the second conductivity type and disposed in the second well, and a fourth doping region having the first conductivity type and disposed in the substrate. The first conductivity type is different from the second conductivity type. The second well, the first well, the substrate and the fourth doping region form a silicon controlled rectifier. Electrostatic discharge current flowing into the first doping region flows to the fourth doping region through the silicon controlled rectifier.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 18, 2023
    Inventors: Wen-Tsung HUANG, Shih-Yu WANG, Chih-Wei HSU
  • Publication number: 20230133016
    Abstract: A thyristor includes a first transistor and a second transistor. The first transistor has a first end serving as an anode end. The second transistor has a control end coupled to a second end of the first transistor, a first end coupled to a control end of the first transistor, and a second end coupled to the first end of the second transistor and serving as a cathode end.
    Type: Application
    Filed: October 28, 2021
    Publication date: May 4, 2023
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Shih-Yu Wang, Wen-Tsung Huang, Chih-Wei Hsu
  • Patent number: 11539206
    Abstract: An input output circuit and an electrostatic discharge (ESD) protection circuit are provided. The ESD protection circuit is adapted to a charged-device model (CDM). The ESD protection circuit includes a bipolar junction transistor (BJT). The BJT has a first end coupled to an input end of an input buffer and an output end of an output buffer. A second end of the BJT is coupled to a first ground rail. A control end of the BJT is coupled to one of a first power rail, a second power rail, the first ground rail and a second ground rail.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: December 27, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Yu Wang, Wen-Tsung Huang, Chih-Wei Hsu
  • Publication number: 20220367304
    Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuoching CHENG, Yuan-Feng CHIANG, Ya Fang CHAN, Wen-Long LU, Shih-Yu WANG
  • Publication number: 20220352146
    Abstract: Methods, systems and apparatus for memory devices with discharging circuits are provided. In one aspect, a semiconductor device includes a semiconductor substrate, one or more discharging circuits arranged on the semiconductor substrate, one or more common source line (CSL) layers conductively coupled to the one or more discharging circuits, and a memory array having a three-dimensional (3D) array of memory cells arranged in a plurality of vertical channels on the one or more CSL layers. Each of the plurality of vertical channels includes a respective string of memory cells, and each of the one or more CSL layers is conductively coupled to corresponding strings of memory cells. Each of the one or more discharging circuits includes one or more transistors that are disabled by one or more corresponding conductive lines through the memory array.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Applicant: Macronix International Co., Ltd.
    Inventors: JUNG CHUAN TING, SHIH-YU WANG, SHAO-CHI CHEN
  • Patent number: 11482520
    Abstract: The present disclosure relates to a semiconductor device, including a first source/drain region, a second source/drain region, a base region, a first electrostatic discharge region and a second electrostatic discharge region. The first source/drain region and the second source/drain region are configured to receive a first power voltage and a second power voltage, and are formed on the base region. The first electrostatic discharge region includes a first doped region and a first well. The first doped region is configured to receive the second power voltage, and formed in the first well. The second electrostatic discharge region includes a second doped region and a second well. The second doped region is configured to receive the first power voltage, and formed in the second well. The first source/drain region and the second source/drain region are disposed between the first electrostatic discharge region and the second electrostatic discharge region.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: October 25, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Yu Wang, Wen-Tsung Huang, Chih-Wei Hsu