Abstract: An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region and a fourth doping region. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the second conductivity is disposed in the first well. The second doping region having the first conductivity is at least partially disposed in the first well and surrounds the first doping region. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The first doping region, the third doping region, the first well and the second well are integrated to form a first parasitic BJT and a second parasitic BJT that have different majority carriers.

Abstract: A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.

Abstract: A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.

Abstract: A semiconductor structure includes a first heavily doped region, a first well, a second well and a second heavily doped region disposed sequentially. The first well and the second heavily doped region have a first conductive type. The second well and the first heavily doped region have a second conductive type. The semiconductor structure further includes at least one switch, such that at least one of conditions (A) and (B) is satisfied. (A) The switch is coupled between the first well and the first node such that the first well is controlled by the switch and floated under an ESD protection mode. (B) The switch is coupled between the second well and the second node such that the second well is controlled by the switch and floated under an ESD protection mode.

Abstract: A semiconductor structure includes a first heavily doped region, a first well, a second well and a second heavily doped region disposed sequentially. The first well and the second heavily doped region have a first conductive type. The second well and the first heavily doped region have a second conductive type. The semiconductor structure further includes at least one switch, such that at least one of conditions (A) and (B) is satisfied. (A) The switch is coupled between the first well and the first node such that the first well is controlled by the switch and floated under an ESD protection mode. (B) The switch is coupled between the second well and the second node such that the second well is controlled by the switch and floated under an ESD protection mode.

Abstract: An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the doping well. The first doping region having a second conductivity, is disposed in the doping well and adjacent to the first gate structure, and is electrically connected to a pad. The second doping region having the second conductivity is disposed in the doping well and adjacent to the first gate structure. The third doping region having the first conductivity is disposed in the doping well and forms a P/N junction interface with the second doping region, wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well.

Abstract: An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region and a fourth doping region. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the second conductivity is disposed in the first well. The second doping region having the first conductivity is at least partially disposed in the first well and surrounds the first doping region. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The first doping region, the third doping region, the first well and the second well are integrated to form a first parasitic BJT and a second parasitic BJT that have different majority carriers.

Abstract: Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.

Abstract: A display apparatus which is also able to receive and identify fingerprints comprises a first substrate, a second substrate, a liquid crystal layer, a plurality of dummy pixel units located in a non-display region, a fingerprint identification module, and a plurality of data extending lines. Each of the dummy units comprises first and second auxiliary electrodes. The fingerprint identification module comprises signal transmitting layer and signal receiving components on the signal transmitting layer. The signal receiving component receives reflected ultrasonic wave and converts the received waves into fingerprint signal. The data extending line is electrically connected with the dummy pixel unit. The signal receiving component transmits the fingerprint signals to the at least one first auxiliary electrode and the data extending line thus receives the fingerprint signal.

Abstract: Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.

Abstract: An electrostatic discharge protection device including a PNP transistor, a protection circuit and an adjustment circuit is provided. An emitter of the PNP transistor is electrically connected to a pad, and a collector of the PNP transistor is electrically connected to a ground. The protection circuit is electrically connected between a base of the PNP transistor and the ground, and provides a discharge path. When an electrostatic signal occurs on the pad, the electrostatic signal is conducted to the ground through the discharge path and the PNP transistor. The adjustment circuit is electrically connected between the emitter and the base of the PNP transistor. When a power voltage is supplied to the pad, the adjustment circuit provides a control voltage to the base of the PNP transistor according to the power voltage, so as to prevent the emitter and the base of the PNP transistor from being forward biased.

Abstract: An electrostatic discharge protection device that includes a plurality of voltage drop elements, an impedance element, a driving circuit, and a clamping circuit is provided. The voltage drop elements are electrically connected in series between a first line and a node, and the voltage drop elements are configured to define an activating voltage. If a signal from the first line is greater than the activating voltage, the voltage drop elements conduct the first line to the node in response to the signal from the first line. The impedance element is electrically connected between the node and a second line. The driving circuit amplifies a control signal from the node and accordingly generates a driving signal. The clamping circuit determines whether to generate a discharging path between the first line and the second line according to the driving signal.

Abstract: A semiconductor device includes a rectifier coupled between a circuit ground and a terminal for coupling to an external circuit, a transistor-enhanced current path coupled to the rectifier, and a switching circuit coupled to the transistor-enhanced current path and coupled between the terminal and the circuit ground. The switching circuit is configured to turn off the transistor-enhanced current path during normal operation, and turn on the transistor-enhanced current path when an electrostatic discharge occurs at the terminal.

Abstract: Disclosed herein is a light guide, which includes a light-receiving surface and a light-emitting surface. The light-emitting surface includes a plurality of gratings spaced apart from each other by a spacing interval. Each grating has a number of prisms extending in a predetermined direction. The predetermined direction of at least one grating is different from that of another grating. These gratings cooperate together to allow light in a wavelength range to transmit the gratings, and to restrict light in another wavelength range to transmit the gratings. An electrophoretic display apparatus switchable between black-white mode and color mode is disclosed as well.

Abstract: An electrostatic discharge (ESD) protection device including a modified lateral silicon-controlled rectifier (MLSCR) and a voltage control circuit is provided. The MLSCR has a first terminal, a second terminal and a control terminal connected to a first P+-type doped region, where the first terminal and the second terminal are electrically connected to a first line and a second line, respectively. The voltage control circuit is electrically connected to the first line, the second line and the control terminal. When an electrostatic pulse is appeared on the first line, the voltage control circuit provides a current path from the first line to the control terminal. When an input signal is supplied to the first line, the voltage control circuit receives a power voltage, and stops providing the current path according to the power voltage.

Abstract: An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body.

Abstract: A semiconductor device includes a rectifier coupled between a circuit ground and a terminal for coupling to an external circuit, a transistor-enhanced current path coupled to the rectifier, and a switching circuit coupled to the transistor-enhanced current path and coupled between the terminal and the circuit ground. The switching circuit is configured to turn off the transistor-enhanced current path during normal operation, and turn on the transistor-enhanced current path when an electrostatic discharge occurs at the terminal.

Abstract: An LED driver having one end coupled with an LED module and another end coupled to a ground, being capable of generating a duty current and a duty in response to a dropout voltage across the LED driver in a way that, the duty current will increase and the duty will decrease when the dropout voltage exceeds a first threshold, and the duty current will decrease and the duty will increase when the dropout voltage falls below a second threshold.

Abstract: A semiconductor device includes a substrate, and first and second wells formed in the substrate. The first well has a first conductivity type. The second well has a second conductivity type different than the first conductivity type. The device includes a first heavily-doped region having the first conductivity type and a second heavily-doped region having the first conductivity type. A portion of the first heavily-doped region is formed in the first well. The second heavily-doped region is formed in the second well. The device also includes an insulating layer formed over a channel region of the substrate between the first and second heavily-doped regions, and a gate electrode formed over the insulating layer. The device further includes a terminal for coupling to a circuit being protected, and a switching circuit coupled between the terminal and the first heavily-doped region, and between the terminal and the gate electrode.

Abstract: A semiconductor device includes a substrate, and first and second wells formed in the substrate. The first well has a first conductivity type. The second well has a second conductivity type different than the first conductivity type. The device includes a first heavily-doped region having the first conductivity type and a second heavily-doped region having the first conductivity type. A portion of the first heavily-doped region is formed in the first well. The second heavily-doped region is formed in the second well. The device also includes an insulating layer formed over a channel region of the substrate between the first and second heavily-doped regions, and a gate electrode formed over the insulating layer. The device further includes a terminal for coupling to a circuit being protected, and a switching circuit coupled between the terminal and the first heavily-doped region, and between the terminal and the gate electrode.