Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.

Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A method for determining performance of an integrated circuit (IC) is disclosed herein. The method includes following operations: disposing hardware performance monitors (HPMs) in each of ICs, in which each of HPMs generates a value for generating the performance of the IC; providing a performance function including of terms according to values generated by the HPMs, in which a weight is associated with each of terms; determining the weight of each of terms according to a first set of ICs of the ICs, wherein the performance of each of the ICs is known; and determining the performance of a first ICs of the ICs according to the performance function, wherein the performance function and the weights are built into the first ICs.

Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.

Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.

Abstract: An aging detection circuit is provided. The aging detection circuit is configured on a chip and includes a testing circuit and an aging signal generation circuit. The testing circuit is electrically coupled to the aging signal generation circuit. The testing circuit generates an output signal. The aging signal generation circuit includes a signal generation circuit and a selection circuit. The signal generation circuit generates multiple input signals having different frequencies. The selection circuit selectively outputs one of the input signals as an aging signal to an input terminal of the testing circuit or feeds back the output signal generated by the testing circuit to the input terminal of the testing circuit.

Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.

Abstract: An integrated circuit includes a main clock tree, a reference clock trunk, a reference clock buffer and a calibration circuit. The main clock tree transmits a main operation clock to an internal node via serially-coupled buffers to form a local clock at an internal node. The reference clock buffer transmits a main reference clock via the reference clock trunk to form a reference clock at a terminal node. The calibration circuit compares phases of the local clock and the reference clock to accordingly generate a control signal, so the main clock tree can adjust phase of the local clock according to the control signal.

Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.

Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.

Abstract: A method of determining the performance of a chip of an integrated-circuit design comprises instantiating a plurality of HPM in the integrated-circuit design to generate the performance of the chip according to a performance function defined by a polynomial comprising a plurality of terms, wherein each term of the polynomial comprises an exponent of a value generated by a corresponding one of the plurality of HPM(s) and a corresponding coefficient, wherein the coefficients are determined through a regression process with sample chips of the integrated-circuit design having known performance, so that the performance of each chip other than the sample chips can be determined by the performance function and the values of the plurality of HPM(s) of the chip.

Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.

Abstract: An integrated circuit includes a main clock tree, a reference clock trunk, a reference clock buffer and a calibration circuit. The main clock tree transmits a main operation clock to an internal node via serially-coupled buffers to form a local clock at an internal node. The reference clock buffer transmits a main reference clock via the reference clock trunk to form a reference clock at a terminal node. The calibration circuit compares phases of the local clock and the reference clock to accordingly generate a control signal, so the main clock tree can adjust phase of the local clock according to the control signal.

Abstract: An aging detection circuit is provided. The aging detection circuit is configured on a chip and includes a testing circuit and an aging signal generation circuit. The testing circuit is electrically coupled to the aging signal generation circuit. The testing circuit generates an output signal. The aging signal generation circuit includes a signal generation circuit and a selection circuit. The signal generation circuit generates multiple input signals having different frequencies. The selection circuit selectively outputs one of the input signals as an aging signal to an input terminal of the testing circuit or feeds back the output signal generated by the testing circuit to the input terminal of the testing circuit.

Abstract: A method for determining performance of an integrated circuit (IC) is disclosed herein. The method includes following operations: disposing hardware performance monitors (HPMs) in each of ICs, in which each of HPMs generates a value for generating the performance of the IC; providing a performance function including of terms according to values generated by the HPMs, in which a weight is associated with each of terms; determining the weight of each of terms according to a first set of ICs of the ICs, wherein the performance of each of the ICs is known; and determining the performance of a first ICs of the ICs according to the performance function, wherein the performance function and the weights are built into the first ICs.