Patents by Inventor Shih-Yao Lin

Shih-Yao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113576
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source/drain region, and a dielectric spacer disposed between the gate electrode layer and the source/drain region. A first portion of the dielectric spacer is in contact with a first portion of the first gate spacer. The structure further includes a sacrificial layer disposed between a second portion of the first gate spacer and a second portion of the dielectric spacer.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chih-Chung CHIU, Chen-Chin LIAO, Chun-Yu LIN, Min-Chiao LIN, Yung-Chi CHANG, Li-Jung KUO
  • Publication number: 20250112137
    Abstract: A method of manufacturing a device includes bonding a first die and a second die to a first side of a substrate, forming a stress buffer structure over the first die and the second die, where the stress buffer structure includes a first portion of a first via extending through a first insulating layer, a second portion of the first via extending through a second insulating layer, and a third portion of the first via extending through a third insulating layer, where the second portion of the first via is disposed between the first portion of the first via and the third portion of the first via, and where a diameter of the second portion of the first via is smaller than diameters of the first portion of the first via and the third portion of the first via, and depositing a metal layer over the stress buffer structure.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Shih-Wei Liu, Po-Yao Lin, Sing-Da Jiang, Tsunyen Wu, Kathy Wei Yan
  • Patent number: 12266715
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
  • Publication number: 20250107207
    Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Chi-Sheng LAI, Wei-Chung SUN, Yu-Bey WU, Yuan-Ching PENG, Yu-Shan LU, Li-Ting CHEN, Shih-Yao LIN, Yu-Fan PENG, Kuei-Yu KAO, Chih-Han LIN, Jing Yi YAN, Pei-Yi LIU
  • Publication number: 20250105077
    Abstract: A package-on-package (PoP) structure includes a first package structure and a second package structure stacked on the first package structure. The first package structure includes a die, conductive structures, an encapsulant, and a conductive pattern layer. The conductive structures surround the die. The encapsulant laterally encapsulates the die and the conductive structures. The conductive pattern layer is disposed over and in physical contact with a top surface of the encapsulant and top surfaces of the conductive structures. An entire bottom surface of the conductive pattern layer is located at a same level height, and an entirety of the top surface of the encapsulant and an entirety of the top surfaces of the conductive structures are located at the same level height.
    Type: Application
    Filed: December 10, 2024
    Publication date: March 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu, Shih-Ting Hung, Yi-Jou Lin, Tzu-Jui Fang, Po-Yao Chuang
  • Patent number: 12261170
    Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • Patent number: 12261172
    Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A plurality of fins is formed extending from the substrate, the fins including a first group of active fins arranged in an active region, and including an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions between adjacent of the active regions, the inactive fin separated from its closest active fin by a second trench region, the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Yi Tsai, Shih-Yao Lin, Chi-Hsiang Chang, Wei-Han Chen, Shu-Yuan Ku
  • Patent number: 12261213
    Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Publication number: 20250092151
    Abstract: Provided herein are tetravalent antibodies that specifically bind to human PSGL-1. Unlike bivalent antibodies, these tetravalent antibodies contain a dimer of two monomers, with each monomer comprising two light chain variable (VL) domains and two heavy chain variable (VH) domains. This format allows for cross-linker/FcR-expressing cell-independent tetravalent antibodies against PSGL-1 that show enhanced efficacy as compared to bivalent PSGL-1 antibodies. These tetravalent antibodies can be used in a variety of diagnostic and therapeutic methods, including without limitation treating T-cell mediated inflammatory diseases, transplantations, and transfusions.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 20, 2025
    Inventors: Rong-Hwa LIN, Shih-Yao LIN, Yu-Ying TSAI
  • Publication number: 20250096071
    Abstract: Provided are integrated circuit systems and methods for fabricating semiconductor packages. An integrated circuit system includes a circuit board having a top side and a bottom side and defining an opening from the top side to the bottom side; a bottom boiling plate having a recessed portion and having a projection with a terminal surface, wherein the recessed portion is located below the bottom side of the circuit board, wherein the projection extends through the opening, and wherein the terminal surface is located above the top side of the circuit board; a semiconductor substrate located over the top side of the circuit board and including semiconductor devices; and a top boiling plate located over the semiconductor substrate, wherein the bottom boiling plate and the top boiling plate are configured to dissipate heat away from the integrated circuit system.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsunyen Wu, Po-Yao Lin, Sing-Da Jiang, Shih-Wei Liu, Kathy Yan
  • Publication number: 20250089328
    Abstract: Semiconductor devices and methods for forming the semiconductor devices using a cap layer are provided. The semiconductor devices include a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers, and a gate spacer that extends along a sidewall of the upper portion of the gate structure. In some examples, a gap dimension measured between the gate spacer and an adjacent one of the plurality of semiconductor layers is sufficiently small such that the gate structure does not contact the source/drain structures. In some examples, the gate spacer and an adjacent one of the one or more semiconductor layers of the fin structure are separated by a cap layer.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chiung-Yu Cho, Chih-Han Lin, Ming-Ching Chang
  • Publication number: 20250084861
    Abstract: A fan shaft structure includes a fan frame having an axle seat set therein with a stator silicon steel sheet set and a circuit board installed outside the axle seat, a fan blade set in the fan frame holds a rotor magnet therein relative to the outside of the stator silicon steel sheet set, and a rotating shaft has one end assembled at the fan blade and its other end assembled in the axle seat. The outer part of the rotating shaft located in an accommodating groove is mounted with bearings, oil-containing members and oil-retaining caps. The oil film on the inner diameter of the oil-containing members can contact the rotating shaft to fill the gap between the oil-containing members and the rotating shaft, which can prevent external environmental dust, fine particles or foreign matter from penetrating between the rotating shaft and the bearings.
    Type: Application
    Filed: May 9, 2024
    Publication date: March 13, 2025
    Inventors: Shih-Jen Lin, Ching-Yao Chen
  • Publication number: 20250081587
    Abstract: A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.
    Type: Application
    Filed: November 14, 2024
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • Publication number: 20250079428
    Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.
    Type: Application
    Filed: November 15, 2024
    Publication date: March 6, 2025
    Inventors: Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai, Shin-Puu Jeng
  • Publication number: 20250081532
    Abstract: A semiconductor device includes an active gate structure extending along a first lateral direction. The semiconductor device includes an inactive gate structure also extending along the first lateral direction. The semiconductor device includes a first epitaxial structure disposed between the active gate structure and the inactive gate structure along a second lateral direction perpendicular to the first lateral direction. The active gate structure wraps around each of a plurality of channel layers that extend along the second direction, and the inactive gate structure straddles a semiconductor cladding layer that continuously extends along a first sidewall of the first epitaxial structure and across the plurality of channel layers.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Ming-Ching Chang
  • Patent number: 12243748
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 12242788
    Abstract: A method includes providing a placing layout of the integrated circuit; generating a routed layout including a layout region with a systematic design rule check (DRC) violation; and performing a loop when the DRC the systematic DRC violation exists. The loop includes: generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe; extracting features of the placing layout to obtain extracted data; extracting features of the layout region with the systematic DRC violation to obtain extracted routing data; generating a plurality of aggregated-cluster models based upon the extracted data and the extracted routing data; selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models; and selecting the target placement recipe from a plurality of placement recipes to generate the adjusted routing layout.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Yao Lin, Yi-Lin Chuang, Yin-An Chen, Shih Feng Hong
  • Publication number: 20250068016
    Abstract: An electronic device is provided. The electronic device includes a first substrate; a second substrate disposed opposite to the first substrate; a liquid crystal layer disposed between the first substrate and the second substrate; a plurality of first electrodes disposed between the first substrate and the liquid crystal layer; a plurality of second electrodes disposed between the second substrate and the liquid crystal layer; a first signal line disposed between the first substrate and the liquid crystal layer, and electrically connected to one of the plurality of first electrodes; and a second signal line disposed between the second substrate and the liquid crystal layer, and electrically connected to one of the plurality of second electrodes. The first signal line and the second signal line include a blackened metal.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Inventors: Ting-Wei LIANG, Jiunn-Shyong LIN, I-An YAO, Tzu-Chieh LAI, Chung-Chun CHENG, Shih-Che CHEN
  • Publication number: 20250072101
    Abstract: A semiconductor device includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and second transistors operate under a lower gate voltage than the third and fourth transistors. The first transistor has a first active gate structure and the second transistor has a second active gate structure. The first and second active gate structures are separated by a first gate isolation structure along a first direction. The third transistor has a third active gate structure and the fourth transistor has a fourth active gate structure. The third and fourth active gate structures are separated by a second gate isolation structure along the first direction. The variation of a first distance between respective sidewalls of the first gate isolation structure is equal to the variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Uei Jang, Shu-Yuan Ku, Shih-Yao Lin
  • Patent number: 12230545
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang