Patents by Inventor Shih-Yao Lin
Shih-Yao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11964520Abstract: A packaging method for a tire pressure monitoring sensor includes a step of placing, a step of pouring, and a step of hardening. In the step of placing, a sensing transmission module is put into a cavity of a modeling unit, and a positioning portion in the cavity restricts the sensing transmission module from moving transversely and toward an inner bottom of the cavity. In the step of pouring, a rubber compound is poured into the cavity and fills the cavity. The sensing transmission module is coated by the rubber compound to form a case on the outer surface of the sensing transmission module. In the step of hardening, the case is hardened and integrally formed with the sensing transmission module to form a tire pressure monitoring sensor which is removed from the cavity.Type: GrantFiled: January 18, 2022Date of Patent: April 23, 2024Assignee: SYSGRATION LTD.Inventors: Sheng-Hao Lee, Shih-Yao Lin
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Patent number: 11967533Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate that both extend along a first direction. The method includes forming a dielectric fin extending along the first direction and is disposed between the first and second semiconductor fins. The method includes forming a dummy gate structure extending along a second direction and straddling the first and second semiconductor fins and the dielectric fin. The method includes removing a portion of the dummy gate structure over the dielectric fin to form a trench by performing an etching process that includes a plurality of stages. Each of the plurality of stages includes a combination of anisotropic etching and isotropic etching such that a variation of a distance between respective inner sidewalls of the trench along the second direction is within a threshold.Type: GrantFiled: June 23, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Uei Jang, Shu-Yuan Ku, Shih-Yao Lin
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Publication number: 20240125982Abstract: A metalens including a transparent substrate and lenses is provided. The lenses are located on the transparent substrate. Each of the lenses includes first columnar microstructures continuously arranged along a first direction and second columnar microstructures continuously arranged along a second direction. A pitch of the first columnar microstructure is different from a pitch of the second columnar microstructure.Type: ApplicationFiled: November 18, 2022Publication date: April 18, 2024Applicant: GUANGZHOU LUXVISIONS INNOVATION TECHNOLOGY LIMITEDInventors: Tzu-Yao Lin, Shih-Chieh Yen
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Patent number: 11961899Abstract: A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.Type: GrantFiled: January 23, 2023Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Chao-Cheng Chen
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Patent number: 11955385Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.Type: GrantFiled: August 27, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Hsiao Wen Lee
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Patent number: 11948581Abstract: A smart interpreter engine is provided. The smart interpreter engine includes a speech to text converter, a natural language processing module and a translator. The speech to text converter is utilized for converting speech data corresponding to a first language into text data corresponding to the first language. The natural language processing module is utilized for converting the text data corresponding to the first language into glossary text data corresponding to the first language according to a game software. The translator is utilized for converting the glossary text data corresponding to the first language into text data corresponding to a second language.Type: GrantFiled: May 18, 2022Date of Patent: April 2, 2024Assignee: ACER INCORPORATEDInventors: Gianna Tseng, Shih-Cheng Huang, Shang-Yao Lin, Szu-Ting Chou
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Patent number: 11942363Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.Type: GrantFiled: August 9, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
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Patent number: 11942529Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.Type: GrantFiled: June 7, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
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Publication number: 20240096893Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
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Publication number: 20240097007Abstract: A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Hsiao Wen Lee, Ya-Yi Tsai, Shu-Uei Jang, Chih-Han Lin, Shu-Yuan Ku
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Publication number: 20240096705Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
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Publication number: 20240084028Abstract: Provided herein are tetravalent antibodies that specifically bind to human PSGL-1. Unlike bivalent antibodies, these tetravalent antibodies contain a dimer of two monomers, with each monomer comprising two light chain variable (VL) domains and two heavy chain variable (VH) domains. This format allows for cross-linker/FcR-expressing cell-independent tetravalent antibodies against PSGL-1 that show enhanced efficacy as compared to bivalent PSGL-1 antibodies. These tetravalent antibodies can be used in a variety of diagnostic and therapeutic methods, including without limitation treating T-cell mediated inflammatory diseases, transplantations, and transfusions.Type: ApplicationFiled: March 13, 2023Publication date: March 14, 2024Inventors: Rong-Hwa LIN, Shih-Yao LIN, Yu-Ying TSAI
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Patent number: 11928415Abstract: A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.Type: GrantFiled: January 23, 2023Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching Hsu, Shih-Yao Lin, Yi-Lin Chuang
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Publication number: 20240077409Abstract: A chiral molecule detector includes a light source, a photodetector, and a carrier. The carrier is configured to reflect at least part of light emitted by the light source to the photodetector. The carrier includes a substrate and a metal reflective layer. An upper surface of the substrate has a periodic hole array containing multiple holes. The metal reflective layer is located on the upper surface of the substrate, and covers a sidewall of the hole and a bottom surface of the hole.Type: ApplicationFiled: November 28, 2022Publication date: March 7, 2024Applicant: GUANGZHOU LUXVISIONS INNOVATION TECHNOLOGY LIMITEDInventors: Tzu-Yao Lin, Shih-Chieh Yen
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Patent number: 11923440Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.Type: GrantFiled: July 26, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
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Patent number: 11908746Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: GrantFiled: August 28, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
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Patent number: 11908903Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.Type: GrantFiled: July 8, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 11908920Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.Type: GrantFiled: April 18, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Publication number: 20240051353Abstract: A mode-swappable tire pressure detection system and a method of operating the same are provided and applied to tires of motor vehicles. The mode-swappable tire pressure detection system has a tire pressure detector. The tire pressure detector has a memory module. The memory module is configured with sensing modes, rendering the tire pressure detector capable of switching between different sensing modes. When a user issues a control instruction to a host or the tire pressure detector, the tire pressure detector can switch between different sensing modes through the memory module.Type: ApplicationFiled: July 25, 2023Publication date: February 15, 2024Inventor: SHIH-YAO LIN
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Publication number: 20240047458Abstract: A FinFET device includes a first fin and a second fin on a substrate, a dielectric fin, a metal gate line, a gate dielectric layer, a gate isolation structure. The dielectric fin is located between the first fin and the second fin. The metal gate line is across the first fin, the dielectric fin and the second fin. The gate dielectric layer is located between the metal gate line and the dielectric fin, between the metal gate line and the first fin, and between the metal gate line and the second fin. The gate isolation structure extends through the first metal gate line and the gate dielectric layer, and landing on the dielectric fin. A top surface of the gate dielectric layer is lower than a top surface of the gate isolation structure.Type: ApplicationFiled: August 5, 2022Publication date: February 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Uei Jang, Shih-Yao Lin