Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: In a first aspect, a module is provided that is adapted to process a wafer. The module includes a processing portion having one or more features such as (1) a rotatable wafer support for rotating an input wafer from a first orientation wherein the wafer is in line with a load port to a second orientation wherein the wafer is in line with an unload port; (2) a catcher adapted to contact and travel passively with a wafer as it is unloaded from the processing portion; (3) an enclosed output portion adapted to create a laminar air flow from one side thereof to the other; (4) an output portion having a plurality of wafer receivers; (5) submerged fluid nozzles; and/or (6) drying gas flow deflectors, etc. Other aspects include methods of wafer processing.

Abstract: Embodiments of the invention generally provide methods for end point detection at predetermined dopant concentrations during plasma doping processes. In one embodiment, a method includes positioning a substrate within a process chamber, generating a plasma above the substrate and transmitting a light generated by the plasma through the substrate, wherein the light enters the topside and exits the backside of the substrate, and receiving the light by a sensor positioned below the substrate. The method further provides generating a signal proportional to the light received by the sensor, implanting the substrate with a dopant during a doping process, generating multiple light signals proportional to a decreasing amount of the light received by the sensor during the doping process, generating an end point signal proportional to the light received by the sensor once the substrate has a final dopant concentration, and ceasing the doping process.

Abstract: Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction.

Abstract: One embodiment of the present invention is a method of fabricating an integrated circuit. The method includes providing a substrate having a metal and dielectric damascene metallization layer and depositing substantially on the metal a cap. After deposition of the cap, the substrate is cleaned with a solution comprising an amine to provide a pH for the cleaning solution of 7 to about 13. Another embodiment of the presented invention is a method of cleaning substrates. Still another embodiment of the present invention is a formulation for a cleaning solution.

Abstract: In a first aspect, a first method of drying a substrate is provided. The first method includes the steps of (1) lifting a substrate through an air/fluid interface at a first rate; (2) directing a drying vapor at the air/fluid interface during lifting of the substrate; and (3) while a portion of the substrate remains in the air/fluid interface, reducing a rate at which a remainder of the substrate is lifted through the air/fluid interface to a second rate. The drying vapor may form an angle of about 23° with the air/fluid interface and/or the second rate may be about 2.5 mm/sec.

Abstract: A carrier head for chemical mechanical polishing is described. The carrier head includes a backing assembly, a housing and a damping material. The backing assembly includes a substrate support surface. The housing is connectable to a drive shaft to rotate with the drive shaft about a rotation axis. In one implementation, the damping material is in a load path between the backing assembly and the housing to reduce transmission of vibrations from the backing assembly to the housing.

Abstract: Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

Abstract: Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: A method is provided for performing plasma immersion ion implantation with a highly uniform seasoning film on the interior of a reactor chamber having a ceiling and a cylindrical side wall and a wafer support pedestal facing the ceiling. The method includes providing a gas distribution ring with plural gas injection orifices on a periphery of a wafer support pedestal, the orifices facing radially outwardly from the wafer support pedestal. Silicon-containing gas is introduced through the gas distribution orifices of the ring to establish a radially outward flow pattern of the silicon-containing gas. The reactor includes pairs of conduit ports in the ceiling adjacent the side wall at opposing sides thereof and respective external conduits generally spanning the diameter of the chamber and coupled to respective pairs of the ports. The method further includes injecting oxygen gas through the conduit ports into the chamber to establish an axially downward flow pattern of oxygen gas in the chamber.

Abstract: An improved deposition chamber (2) includes a housing (4) defining a chamber (18) which houses a substrate support (14). A mixture of oxygen and SiF4 is delivered through a set of first nozzles (34) and silane is delivered through a set of second nozzles (34a) into the chamber around the periphery (40) of the substrate support. Silane (or a mixture of silane and SiF4) and oxygen are separately injected into the chamber generally centrally above the substrate from orifices (64, 76). The uniform dispersal of the gases coupled with the use of optimal flow rates for each gas results in uniformly low (under 3.4) dielectric constant across the film.

Abstract: The present invention pertains to methods, apparatuses, and systems for fabricating three-dimensional integrated circuits. One embodiment of the method comprises providing a wafer or other substrate having a plurality of through holes. In addition, the method includes supporting the wafer or other substrate with a wafer or other substrate holder mounted in a process chamber. The method further includes generating a pressure differential between the front side of the wafer or other substrate and the back side of the wafer or other substrate while the wafer or other substrate is supported on the wafer or other substrate holder so that the pressure differential causes fluid flow through the through holes. Also, the method includes establishing process conditions in the process chamber for at least one process to fabricate integrated circuits. Embodiments of a system and embodiments of an apparatus according to the present invention are also presented.

Abstract: The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition.

Abstract: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, the method for implanting ions into a substrate by a plasma immersion ion implantation process includes providing a substrate into a processing chamber, supplying a gas mixture including a reacting gas and a reducing gas into the chamber, and implanting ions from the gas mixture into the substrate. In another embodiment, the method includes providing a substrate into a processing chamber, supplying a gas mixture including reacting gas and a hydrogen containing reducing gas into the chamber, and implanting ions from the gas mixture into the substrate.

Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.

Abstract: Compositions and methods for removal of barrier layer materials by a chemical mechanical polishing technique are provided. In one aspect, the invention provides a composition adapted for removing a barrier layer material in a chemical mechanical polishing technique including at least one reducing agent selected from the group of bicarboxylic acids, tricarboxylic acids, and combinations thereof, at least one reducing agent selected from the group of glucose, hydroxylamine, and combinations thereof, and deionized water, wherein the composition has a pH of about 7 or less. The composition may be used in a method for removing the barrier layer material including applying the composition to a polishing pad and polishing the substrate in the presence of the composition to remove the barrier layer.

Abstract: A carrier head for chemical mechanical polishing, includes a base, a support structure attached to the base having a surface for contacting a substrate, and a retaining structure attached to the base to prevent the substrate from moving along the surface. The retaining structure and the surface define a cavity for receiving the substrate. A polishing station includes a platen, a vibration damper mounted on the platen and a substrate polishing pad mounted on the vibration damper. The vibration damper includes a material that does not rebound to its original shape when subjected to a deformation.

Abstract: In a first aspect, a module is provided that is adapted to process a wafer. The module includes a processing portion having one or more features such as (1) a rotatable wafer support for rotating an input wafer from a first orientation wherein the wafer is in line with a load port to a second orientation wherein the wafer is in line with an unload port; (2) a catcher adapted to contact and travel passively with a wafer as it is unloaded from the processing portion; (3) an enclosed output portion adapted to create a laminar air flow from one side thereof to the other; (4) an output portion having a plurality of wafer receivers; (5) submerged fluid nozzles; and/or (6) drying gas flow deflectors, etc. Other aspects include methods of wafer processing.

Abstract: A chemical-mechanical polishing composition that includes less than about 1% wt. abrasive, an additive, and water, where a weigh percent of the additive is greater than a weight percent of the abrasive. Also, a method of polishing a semiconductor substrate in a shallow trench isolation process, the method including contacting the substrate with a polishing pad of a polishing apparatus while applying a high selectivity slurry to the polishing pad, where the slurry comprises less than about 1% wt. abrasive, an additive, and water, and where a weigh percent of the additive is greater than a weight percent of the abrasive. Also, a method of making a chemical-mechanical polishing slurry composition, the method including adding together an abrasive, an additive and water to form the slurry, where a weigh percent of the additive is greater than a weight percent of the abrasive, and the abrasive and additive together comprise less than 2% by wt. of the slurry.